Intel’s new GPU D-series puts 160 GB of LPDDR5X on a single PCIe card, while AMD’s Instinct MI355X carries 288 GB of HBM3E running at 8 TB/s. That contrast defines the AI inference GPU debate this month. Intel dropped the Crescent Island code name on October 12 and began pitching a card that partners can build with up to 480 GB of LPDDR5X, as TechPowerUp reported. AMD answered with a steady run of software proof points for a chip that already sits in cloud racks.
The two companies are not chasing the same buyer with the same trade-off. Intel is betting that capacity per dollar matters more than raw bandwidth for serving big language models. AMD is betting that bandwidth and an established ROCm stack still win deployments. Neither bet has been settled by independent benchmarks, and neither company has published a price for the parts being compared.
This analysis lines up the published numbers, shows the arithmetic those numbers imply, and flags what nobody can verify yet. It also places the news against AMD’s recent record, including the MI355X rollout in Saudi Arabia, because deployment evidence is the one area where AMD leads by a wide margin today.
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What Intel Announced for the GPU D-Series
Intel named the product the Intel GPU D-series at the Open Compute Project Global Summit on October 12, 2026. The code name Crescent Island is now history. Intel describes the part as an inference-optimized data-center GPU built on its Xe3P architecture. The reference design is a standard PCIe card with air cooling and a 350 W power envelope, and it carries 32 Xe3P cores and 256 XMX matrix engines.
Memory is the headline. The Intel-branded card has 160 GB of LPDDR5X, and the design lets partners build their own boards with up to 480 GB. Intel cites up to 1.5 TB/s of memory bandwidth and up to 1.3 PFLOPS of FP8 compute. A product page that surfaced on October 13 uses the model name D270 and lists the 480 GB ceiling.
Status matters as much as specs. Intel calls this AI inference GPU “upcoming,” and customer sampling is underway. The company has not confirmed general availability, a ship date, or a price. Our earlier debut coverage of the D-series walked through the launch-day details, so this piece concentrates on how the memory choice stacks up against AMD’s shipping accelerator.
Memory Capacity: 160 GB Against 288 GB Per Card
On a card-to-card basis, AMD holds the capacity lead. The MI355X carries 288 GB of HBM3E, which is 1.8 times the 160 GB on Intel’s own board. That ratio flips only when a partner builds a 480 GB version, which would hold roughly 1.7 times what an MI355X holds.
The node-level picture shifts again. AMD’s published configurations use eight MI355X GPUs in one node, which adds up to 2,304 GB of GPU memory. Eight Intel reference cards would total 1,280 GB, and eight 480 GB partner cards would reach 3,840 GB. Those totals come from simple multiplication of the vendors’ per-card figures, not from a tested system, and Intel has not announced an eight-card reference node with those exact numbers.
Capacity decides which models fit without sharding across many cards. Sharding adds interconnect traffic, software complexity, and latency. A buyer who can serve a model on one or two cards often saves more in engineering time than the sticker price suggests. That is the argument behind Intel’s pitch, and it explains why the 480 GB partner option draws so much attention even though Intel’s own card sits lower.
The Bandwidth Gap: 1.5 TB/s Against 8 TB/s
Bandwidth is where the comparison turns hard for Intel. The MI355X moves up to 8 TB/s from its HBM3E stacks. The D-series tops out at up to 1.5 TB/s from LPDDR5X. Divide one by the other and AMD’s card offers about 5.3 times the memory bandwidth.
Token generation in large language models is largely a memory-bound job. Each new token requires the chip to read the active model weights from memory. A card with more bandwidth reads them faster, so a single request finishes sooner. A card with more capacity but less bandwidth can hold a bigger model yet generate tokens more slowly for each user.
Back-of-envelope decode ceilings
The table below turns the vendor figures into a rough ceiling. It assumes the card’s memory is completely full of model weights and that a single request must read all of them for every token. Real models, especially mixture-of-experts designs, read only part of their weights per token. Batching, caching, and speculative decoding also change the picture. Treat the output as a way to compare memory systems, not as a forecast of any product’s performance.
| Configuration | Capacity | Bandwidth | Time to read all memory once | Single-stream ceiling (tokens/s) |
|---|---|---|---|---|
| Intel D-series, Intel-branded card | 160 GB | Up to 1.5 TB/s | About 107 ms | About 9.4 |
| Intel D-series, 480 GB partner design | 480 GB | Up to 1.5 TB/s | About 320 ms | About 3.1 |
| AMD Instinct MI355X | 288 GB | 8 TB/s | About 36 ms | About 27.8 |
The pattern is clear even with generous caveats. A full 480 GB Intel board takes almost nine times longer to sweep its memory than an MI355X. Intel’s real-world answer is concurrency. Serving many users at once lets the same weight read feed many tokens, which narrows the gap. The company markets the part for long-context work, retrieval-augmented generation, coding assistants, and high-concurrency serving, which are the workloads where that trade makes sense.
Side-by-Side Specifications
The next table gathers the published specifications in one place. Where a figure was not available from the company materials used for this article, the cell says so instead of guessing.
| Attribute | Intel GPU D-series | AMD Instinct MI355X |
|---|---|---|
| Former code name | Crescent Island | Not applicable |
| Architecture | Xe3P, 32 cores, 256 XMX engines | CDNA 4, multi-chiplet design |
| Memory type | LPDDR5X | HBM3E |
| Memory per card | 160 GB (Intel card), up to 480 GB (partners) | 288 GB |
| Memory bandwidth | Up to 1.5 TB/s | 8 TB/s |
| FP8 compute | Up to 1.3 PFLOPS | Not cited in this article |
| Form factor | PCIe, 350 W, air cooled | Data-center accelerator, eight per node in AMD’s cited setups |
| Software stack | Open frameworks and inference engines, day-0 Muse Spark Open support | ROCm, vLLM, SGLang, ATOM, day-0 Muse Spark Open support |
| Availability | Upcoming, customer sampling underway | Deployed in production clusters |
| Published price | None | None found in the sources used |
The compute row shows the limits of a spec-sheet comparison. Intel publishes a peak FP8 figure, yet no matched-workload test sets the D-series against the MI355X. Peak FLOPS rarely predict inference throughput on their own, because memory systems and software maturity usually set the real limit.
Why Intel Chose LPDDR5X Over HBM
High-bandwidth memory is expensive and scarce. Only a few suppliers make it, and its stacking and packaging steps limit how many accelerators the industry can build. LPDDR5X is a mainstream memory type that phones and laptops already consume in volume. Intel is trading peak bandwidth for cheaper, more available capacity in its AI inference GPU.
The timing helps that argument. Buyers have spent months competing for accelerator supply, and our look at the HBM4 shortage and its price jump shows how tight the premium memory market has become. Futurum Group published a piece titled Intel D-Series GPUs Make HBM Optional for AI Inference, which captures the pitch in one line.
The risk is that HBM-class bandwidth is exactly what makes a modern accelerator feel fast. If customers judge cards by latency for a single user, the D-series loses. If they judge by cost per million tokens at high concurrency, the argument gets much closer. Intel has not published cost-per-token data, so that debate stays open.
What Fits on One Card, and What Does Not
Intel says the D-series supports models of up to 300 billion parameters on one card and more than one trillion parameters in an eight-GPU system. Those claims only work with compressed weights. At 4-bit precision a parameter takes half a byte, so 300 billion parameters need about 150 GB, which squeezes into a 160 GB card with little room left for the key-value cache. That precision assumption is our arithmetic, not an Intel disclosure.
Intel’s own October 15 demonstration used four D-series GPUs with 160 GB each, for 640 GB in total, to run Meta’s Muse Spark Open. Intel reportedly said that four-card system could host a model of about 816 billion parameters. At 4-bit weights such a model needs roughly 408 GB, leaving about 230 GB for the cache and runtime overhead. The math is plausible, but the 816 billion figure comes from a single source and deserves caution.
AMD’s equivalent claim rests on a node of eight MI355X GPUs. Its Muse Spark Open support covers the MI355X and MI350X through ROCm and vLLM, with BF16, MXFP4, and FP8 variants, and the reported configuration used eight GPUs in a single node. AMD publishes its day-0 support notes for Muse Spark Open on its developer site. Eight cards at 288 GB each offer far more room for long contexts than four Intel cards, though at a much higher bandwidth bill and presumably a higher price.
AMD’s October: The Software Evidence Behind the MI355X
AMD spent the second half of October stacking up evidence that the MI355X is a working product. On October 15 it announced day-zero support for Muse Spark Open. On October 20 it described EAGLE-4 speculative decoding running on the MI355X from day one through SGLang and ATOM. Both items show a vendor keeping pace with new model releases within hours, which is the standard that matters to cloud operators.
A third item stands out for its specificity. AMD’s Nunchux case study used eight MI355X GPUs to generate video with MiniMax-H3. AMD reported 1.33 seconds for a five-second clip and 5.39 seconds for a 15-second clip, faster than playback. AMD also said the numbers came from an optimized, AMD-supported software stack and not from an unqualified raw-hardware test. That caveat is worth keeping, and it applies to nearly every vendor benchmark in this segment.
For readers tracking the wider accelerator field, our earlier NVIDIA Blackwell against AMD MI350 comparison covers the architecture lineage that the MI355X sits in. The short version is that AMD now competes on rack-level availability and software cadence, not only on chip specs. Intel has no equivalent track record in this product class yet.
Where the MI355X Is Actually Deploying
Cloud provider Vultr said on October 21 and 22 that it plans to place MI355X GPUs in a new 20 MW supercluster in Chennai, India. The company described it as India’s largest AMD Instinct deployment, and ANTARA News carried the announcement. Vultr’s roadmap also references planned future capacity built on the MI455X and AMD’s Helios rack-scale design in 2027. Those parts are plans, not shipping products.
Europe is following a similar path. According to Scaleway’s announcement, the French provider is building a Swedish AI supercomputer on MI355X GPUs, which it reportedly calls its first supercomputer deployment outside France. We treat the October 13 timing as reported, since that detail sits on a single source.
India has become a crowded arena for accelerator orders. Our report on AM Intelligence’s order of 20,000 NVIDIA Rubin GPUs shows the incumbent is also pushing hard into the same market. For Intel, the lesson is that sampling a card in the second half of 2026 puts it behind rivals who already have megawatt-scale sites under contract.
October 2026 Timeline: Six Dated Moves
The month moved fast, and the order of events shows who reacted to whom. The table lists only dated items that appear in company or press materials we could confirm.
| Date (2026) | Event | Company |
|---|---|---|
| Oct. 12 | Crescent Island renamed GPU D-series at OCP Global Summit | Intel |
| Oct. 15 to 16 | Day-0 support for Muse Spark Open announced on both platforms | Intel and AMD |
| Oct. 19 to 24 | Nunchux video-generation case study on eight MI355X GPUs | AMD |
| Oct. 20 | EAGLE-4 support on MI355X via SGLang and ATOM | AMD |
| Oct. 21 | x86 AI-development collaboration around PyTorch announced | Intel with AMD |
| Oct. 21 to 22 | Vultr plans 20 MW MI355X supercluster in Chennai | Vultr and AMD |
The October 21 item is the odd one out. Intel announced a collaboration with AMD to simplify AI development on x86 CPUs using PyTorch. The two companies are rivals in server processors, as our AMD against Intel CPU comparison shows, yet they share an interest in keeping PyTorch portable away from a single GPU vendor.
Market Impact: Who Gains and Who Loses
NVIDIA remains the incumbent in AI accelerators, and nothing announced this month changes that on its own. The D-series does not target the training clusters where HBM bandwidth is non-negotiable. It targets the inference tier, where operators run models for paying users and care about cost per token. That tier is growing fast, and a credible third supplier gives buyers negotiating leverage even if few of them buy the third supplier’s cards.
AMD gains from the framing. A debate over memory capacity versus bandwidth lets it point to 288 GB and 8 TB/s on the same part, a combination Intel does not match. AMD also benefits from Intel validating the inference-first product category. Our overview of who makes GPUs besides NVIDIA and AMD shows how rarely a third data-center vendor has earned real share.
Memory makers also win. Every accelerator sold, whether HBM or LPDDR5X, consumes DRAM that suppliers are already struggling to produce. Enterprise buyers win if cheap capacity forces vendors to compete on cost per token. For broader coverage of GPUs, chips, and storage, the hardware section tracks the segment as it moves.
Historical Context: From Code Name to Product
Intel first described Crescent Island as a 160 GB LPDDR5X inference product in October 2025, with customer sampling planned for the second half of 2026, according to a single-source recap. October 2026 is the moment the company has delivered on that plan, at least at the sampling stage. At Hot Chips 2026 on August 24, the company reportedly showed the same architecture with 32 Xe cores, 256 XMX engines, and up to 480 GB of memory.
The road there was not smooth. We previously covered the schedule slip around Crescent Island and what it implied for Intel’s data-center GPU credibility. A sampling announcement does not erase that history. Customers will want proof that the software works at scale before they commit.
AMD’s MI355X has a shorter but cleaner story. It was reportedly available from September 2025, and AMD has kept adding model support, benchmark entries, and cloud sites ever since. The chip is an active product in October 2026 with no sign of retirement, and Vultr’s roadmap points to the MI455X and Helios racks in 2027.
What Buyers Still Cannot Know
Three gaps limit any serious purchasing decision today. First, neither Intel nor the sources used here list a price for the 160 GB D-series card or its 480 GB partner variants. AMD’s MI355X pricing also did not appear in the official material we reviewed.
Second, no matched-workload benchmark compares the two parts. AMD’s posted results use its own optimized stack. Intel’s demonstration shows that Muse Spark Open runs on four cards, not how fast. Until a neutral party runs the same model at the same precision on both, any claim of one beating the other is speculation.
Third, availability is open. Intel says sampling is underway and has not confirmed when volume shipments begin. Buyers planning 2027 capacity must decide whether to wait for a part that has no date, or to commit to one that is already installed in clusters.
Five Predictions for the Inference Hardware Race
These are our judgments, drawn from the evidence above. They are not company statements.
- Cost per token will replace peak FLOPS as the headline metric. Intel’s capacity-first design only looks good on that measure, so expect its marketing to shift there once benchmarks arrive.
- Partner 480 GB boards will draw more attention than Intel’s own 160 GB card. The larger configuration is the one that separates the D-series from every rival on capacity.
- AMD will keep widening the software gap in the near term. Day-0 model support within hours of a release is hard to match, and AMD has made it routine.
- Neutral benchmarks will favor AMD on latency and Intel on cost, if Intel prices aggressively. A higher price would remove Intel’s only structural argument.
- The MI455X and Helios racks will reset the comparison in 2027. Any purchase made on October 2026 specs will face a newer AMD generation within a year.
Frequently Asked Questions
What is the Intel GPU D-series?
It is Intel’s inference-optimized data-center GPU, formerly code-named Crescent Island. It uses the Xe3P architecture on a 350 W air-cooled PCIe card, with 160 GB of LPDDR5X on Intel’s own board and up to 480 GB on partner designs.
Is the Intel GPU D-series available to buy?
Not yet. Intel calls the product upcoming, and customer sampling is underway. The company has not announced general availability or a price as of October 25, 2026.
How much memory bandwidth does each chip offer?
Intel cites up to 1.5 TB/s for the D-series. AMD lists 8 TB/s for the Instinct MI355X. That makes the AMD card about 5.3 times faster at moving data from memory, on paper.
Which AI inference GPU is better for large language models?
No independent test answers that yet. The MI355X has more bandwidth and a proven software stack. The D-series may offer more capacity per dollar, particularly in 480 GB partner designs, but Intel has published no price or throughput results.
Why does Intel use LPDDR5X instead of HBM?
LPDDR5X is cheaper and easier to source than high-bandwidth memory. Intel trades peak bandwidth for larger capacity, aiming at long-context and high-concurrency inference where fitting the model matters most.
Does the MI355X support Meta’s Muse Spark Open?
Yes. AMD announced day-zero support for Muse Spark Open on the MI355X and MI350X using ROCm and vLLM. The reported configuration used eight GPUs in a single node. Intel announced day-0 support for the model on its own platforms, including the upcoming D-series.
Will AMD’s next generation make the MI355X obsolete?
Not soon. The MI355X remains an active product being deployed in October 2026. Vultr’s roadmap references MI455X and Helios capacity for 2027, but those parts are plans and not shipping hardware.
