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[Simulator] Add high-fidelity CPU-based inference simulator - #33824

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sgl-project:mainfrom
littlefatfat:sglang-simulator-v0.5.16-adaptation
Sep 4, 2026
Merged

hzh0425 merged 8 commits into
sgl-project:mainfrom
littlefatfat:sglang-simulator-v0.5.16-adaptation

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@littlefatfat

@littlefatfat littlefatfat commented Aug 6, 2026 •

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Motivation

This PR introduces SGLang Simulator, a CPU-based inference simulator for
evaluating SGLang scheduling, latency, throughput, and prefix-cache behavior
without loading model weights or executing model kernels.

It is a current-main rework of the simulator prototype in
#22250, while retaining
SGLang v0.5.16 as the tested compatibility floor.

Large-scale inference configuration studies are expensive to run directly on
accelerators. SGLang Simulator reuses the real SGLang scheduler, radix cache,
hierarchical cache, and request lifecycle, while replacing model-forward
execution with a latency predictor. It supports measured traces, synthetic
workloads, and both in-process and HTTP serving workflows.

What This PR Adds

  • Add tools/sglang-simulator as a monorepo component.
  • Reuse the SGLang scheduler, cache allocator, radix cache, hierarchical cache,
    and request lifecycle with dummy model weights and a minimal KV allocation.
  • Add three forward-latency predictors:
    • AIConfigurator;
    • an sklearn-compatible ML predictor;
    • batch-composition replay.
  • Support Random, ShareGPT, and timestamped Autobench workloads.
  • Support direct Python execution through SGLangBenchmarkRunner.
  • Support server and benchmark-client execution through the HTTP serving path.
  • Collect request, latency, throughput, prefix-cache, cache-tier, and predictor
    metrics.
  • Add reusable example configurations, workloads, tokenizer assets, and replay
    fixtures.
  • Add compatibility checks for SGLang launch and serving APIs.
  • Run the simulator regression suite from CPU PR CI when
    tools/sglang-simulator changes.

Simulation Modes

The simulator provides two execution modes:

  • OFFLINE: advances a logical clock without sleeping, intended for fast
    configuration and workload studies.
  • BLOCKING: sleeps for predicted forward latency and visible L2-to-L1 load
    latency, intended for serving-path and timing-semantics validation.

Replay replaces model-forward latency only. CPU preprocessing and
postprocessing overhead remain enabled by default.

For OFFLINE runs, latency, throughput, and duration should be read from the
server-side simulator metrics rather than benchmark-client wall-clock time.

Accuracy Validation

The following results compare simulator output with measured serving traces.
Latency, throughput, and duration values are absolute percentage errors.
Prefix reuse is reported as absolute percentage-point error.

The SGLang baseline column identifies the version used by the real service
that produced the measurement trace.

Model SGLang baseline Hardware Predictor / coverage TTFT TPOT ITL Input throughput Duration Prefix reuse
Qwen3-8B v0.5.9 H20 AIConfigurator; no-cache, L1, and L2 cases 2.38–4.15% 1.64–4.05% 1.78–4.07% 1.41–2.40% 1.39–2.33% 0.00–0.04 pp
Qwen3-32B-FP8 v0.5.9 H20 AIConfigurator; no-cache, L1, and L2 cases 2.40–3.05% 0.58–1.11% 0.52–1.02% 0.52–1.13% 0.51–1.12% 0.00–0.04 pp
GLM-5.1-FP8 v0.5.11 GPU ML; L1 and L2 cases 5.27% N/A N/A 1.11% 1.08% 0.028 pp
DeepSeek-V4-Pro v0.5.11 GPU ML; L1 and L2 cases 6.12% N/A N/A 0.23% 0.22% 0.048 pp
DeepSeek-V4-Flash v0.5.16 GPU ML; L1 case 0.786–1.343% N/A N/A 0.000212% 0.000212% 0.000 pp
DeepSeek-V4-Pro v0.5.16 GPU AIConfigurator; L2, 32–128K traces 1.99–10.17% N/A N/A 0.0055–0.0183% 0.0055–0.0183% 0.000–0.011 pp

TPOT and ITL are not applicable to the GLM-5.1-FP8,
DeepSeek-V4-Pro, and DeepSeek-V4-Flash validation traces because they use
one-token outputs(Prefill-Decode Disaggregation).

aic-accuracy-32-128k-pr

The SGLang v0.5.16 validation additionally covers four measured 32–128K
serving traces. Using AIConfigurator as the forward-latency predictor, the
simulator achieves a mean-TTFT MAPE of 5.89%. Duration and input-throughput
MAPE are both 0.011%, while the maximum absolute prefix-reuse error remains
below 0.011 percentage points.

Prefix-cache accuracy is particularly sensitive to max_total_tokens. This
value determines simulated device KV-cache capacity and also affects
hierarchical host-cache sizing and eviction behavior. For deployment-faithful
comparisons, use the max_total_num_tokens value reported by the real SGLang
server startup log as the simulator's --max-total-tokens value.


CI States

Latest PR Test (Base): ⏳ Run #33785893262
Latest PR Test (Extra): 🚫 Run #33830599147
Latest PR Test (AMD ROCm 7.2): ➖ No AMD PR run found for this commit.

@github-actions github-actions Bot added documentation Improvements or additions to documentation dependencies Pull requests that update a dependency file hicache Hierarchical Caching for SGLang labels Aug 6, 2026
@hzh0425 hzh0425 added run-ci CI: run the baseline test suite on this PR run-ci-extra CI: also run the extra suite (requires run-ci) labels Aug 6, 2026
@hzh0425

hzh0425 commented Aug 6, 2026

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should fix the lint

@littlefatfat littlefatfat mentioned this pull request Aug 6, 2026
6 of 16 tasks
@littlefatfat
littlefatfat force-pushed the sglang-simulator-v0.5.16-adaptation branch 15 times, most recently from afec358 to 85abcc1 Compare August 11, 2026 08:57
@littlefatfat
littlefatfat force-pushed the sglang-simulator-v0.5.16-adaptation branch from 3d877c6 to fd4918e Compare September 3, 2026 03:54
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/rerun-failed-ci

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/rerun-failed-ci

littlefatfat and others added 7 commits September 3, 2026 22:28
Introduce packaging and worker bootstrap, simulator configuration and state, hook primitives, accelerator and model specifications, and AIC, ML, and replay latency predictors.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Add random and Autobench workload parsing together with shared benchmark configuration and the serving benchmark entry point.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Add simulator-aware scheduler, model runner, memory allocators, HiCache and Unified Radix Tree adapters, server launch support, request metrics, and kernel hooks.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Document installation and simulator workflows, and provide reproducible configs, workloads, tokenizer data, replay data, and a small ML predictor asset.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Cover runner and serving parity, OFFLINE and BLOCKING semantics, replay cache hits, reusable assets, and register the compatibility suite in CPU PR CI.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Move simulator compatibility coverage to the opt-in extra workflow so failures remain visible without gating the base SGLang test path. Keep the simulator runtime single-process while preserving modeled parallelism in simulator configuration, and drop the redundant parallelism unit test.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Cast paged decode indices before assigning int32 free pages, and cover a page-boundary decode with output_length greater than one. Keep cache-tier assertions in the cache-specific suite and support both current and legacy HiCache host-pool interfaces.

Move the simulator-aware serving benchmark to benchmark/simulator and keep its source path wired into the extra CPU CI gate.

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
@littlefatfat
littlefatfat force-pushed the sglang-simulator-v0.5.16-adaptation branch from 4858539 to 6bbf550 Compare September 3, 2026 14:44
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/rerun-failed-ci

Comment thread tools/sglang-simulator/setup.py
Comment thread tools/sglang-simulator/src/sglang_simulator/hook/class_hook_entry.py Outdated
Comment thread .github/workflows/_pr-test-simulator-cpu.yml
@ispobock

ispobock commented Sep 3, 2026

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we also need to add a CODEOWNERS entry for tools/sglang-simulator/

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
@littlefatfat

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/rerun-failed-ci

@hzh0425

hzh0425 commented Sep 4, 2026

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we also need to add a CODEOWNERS entry for tools/sglang-simulator/

let me add in next pr

@hzh0425 hzh0425 added run-ci-extra CI: also run the extra suite (requires run-ci) and removed bypass-fastfail run-ci-extra CI: also run the extra suite (requires run-ci) labels Sep 4, 2026
@hzh0425

hzh0425 commented Sep 4, 2026

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image image The CI for the simulator has finished running, and most of the tests for `basea`/`baseb` within `base` have already been executed.

This PR introduces a separate, new directory and does not modify any other code.

@hzh0425
hzh0425 merged commit 59799a3 into sgl-project:main Sep 4, 2026
319 of 394 checks passed
@hzh0425 hzh0425 mentioned this pull request Sep 4, 2026
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StevenChenSE pushed a commit to StevenChenSE/sglang that referenced this pull request Sep 6, 2026
…ect#33824)

Co-authored-by: zhouhaizhu.zhz <zhouhaizhu.zhz@alibaba-inc.com>
Co-authored-by: LinSiyuan814 <linsiyuan.lsy@alibaba-inc.com>
Co-authored-by: hzh0425 <hzh0425@apache.org>
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5 participants