Problems of getting your radioberry to work!!

Visual inspection:

Check with a microscope or camera the pins for bridges and look if they are all connected to the board.

Total current: Monitor the current before proceed, this is a good indication if something went wrong. The total current draw must between .... and ..... mA

Use a 'standalone' radioberry release; choose the latest from https://github.com/pa3gsb/Radioberry-2.x/releases

Radioberry supporting clock

(source code can be found in: https://github.com/pa3gsb/Radioberry-2.x/tree/master/software/rb-clock)

Use of clock:	  

This program sets the (fysical pin 7) GPCLK0 pin to 10 Mhz.

This supporting clock is used for:
	-) reset handler
	-) iambic (cw keying) 
	-) heartbeat
	-) ad9866 spi controlling

It is an important clock but the timing is not used for the ADC and DAC conversions.

This program must be called (clock must be set first) before loading the firmware.

How to measure the supporting clock:

• use a scope
• frequency meter
• gpio-monitor program

Get program from (will place it also in a future release) https://github.com/pa3gsb/Radioberry-2.x/tree/master/software/gpio-monitor

After running sudo ./rb-clock ;

The clock must be available at pin 7 of the rpi.

This must be working before going to the next step, can be tested with or without the radioberry installed.

Loading FPGA 

For loading the FPGA a program is created called 'loadFPGA'.

(source code can be found in: https://github.com/pa3gsb/Radioberry-2.x/tree/master/software/firmwareloader )

Radioberry can be used with a CL016 or a CL025 Cyclone 10 device.

sudo ./loadFPGA CL016 or CL025

If there are problems with programming the FPGA please check:

• is the back plane of the FPGA soldered to ground?
• Are R301 and R302 in place?

Hereby a short description of the FPGA pins used for programming.

MSEL0, MSEL1, MSEL2 ; selecting programming mode; all low; soldered to ground. This programming mode makes it possible to do the programming via the rpi.

FPGA input pin 13; data[0] configuration data bit The rbf file, Raw Binary File, we are sending bit for bit to the FPGA! Executed by loadFPGA program!

FPGA input pin 12; dclk configuration clock the configuration data bit is shifted in the FPGA at the clock rising-edge Executed by loadFPGA program!

FPGA input pin 14; nconfig When asserted (i.e. when it goes low - this is an active low pin), the FPGA is reset-ed and looses its configuration. If the FPGA was in user-mode, it stops operation immediately, and all IOs become inactive. Set during execution by loadFPGA program!

FPGA output pin 9; nstatus This pin indicates when the FPGA is ready to start the configuration process (it takes a few milliseconds for the FPGA to get ready). Read status is executed by loadFPGA program!

FPGA output pin 92; confdone When high, indicates that the FPGA is configured (i.e. in user-mode). Read status is executed by loadFPGA program!

The loadFPGA program indicates if the loading was succesfull. Look carefully to the output of the program.

This must be working before going to the next step.

Check running FPGA image.

How to check if the FPGA image is running correctly?

• scope
• gpio-monitor program
• simple voltage meter

pin 32 is blinking with a frequency of 1 Hz

This must be working before going to the next step.

AD9866

The FPGA is doing an initialisation of the AD9866, the 10Mhz clock is supporting this process.

One important initialisation step of the AD9866 is doubling the frequency using an internal PLL circuit.

!!So before doing this check the previous steps must be executed!!!

How to check if the AD9866 is initialized and running correctly?

• scope
• gpio-monitor program
• simple voltage meter

pin 16 is blinking with a frequency of 1 Hz (This pin 16, check for the clock of the AD9866, is doing the same as pin 32 is doing for the 10 Mhz clock check.)

This must be working before going to the next step.

If this test is not succesfull you need to do following:

Use the KICAD schematic and board layout!!

Measure radio master clock X400 is delivering 38.4Mhz to pin 57 of the AD9866.

The pin 19 of the AD9866 clkout1 must be 76.8Mhz.

If the clock at pin 19 is still 38.4Mhz it seems that the AD9866 is not initialized by the FPGA, this initialisation will be done by a SPI connection (pin 20, 21, 22 and 23 of AD9866) are these pins soldered well? same can be asked for the FPGA site (pin 65, 66, 67 and 68).

XXXXX Further checks xxxxxxxxx