[hipBLASLt][TensileLite] PGR2 + ScheduleLocalWrite=0 kernels drop main-loop global reads #14377

TensileLite kernels with PrefetchGlobalRead >= 2 and ScheduleLocalWrite = 0 have no global loads in the unrolled main loop. They give wrong results once K spans more than 2 DepthU tiles, and they benchmark unrealistically fast. SIA1 + 1LDSBuffer = 1 requires ScheduleLocalWrite = 0, so all such kernels are affected.

Cause: with PGR >= 2, prepareGRInstToSched (tensilelite/Components/SIA.py) defers the next tile's global reads to itemsGRToSchedLater, to be issued after the local writes. Only schedLocalWrite consumes that list. With ScheduleLocalWrite = 0, noSchedLocalWrite runs instead and the reads are dropped.

Reproducer (gfx11, fp16 TN): MT64x64x32 WMMA, ScheduleIterAlg 1 or 2, PrefetchGlobalRead: 2, PrefetchLocalRead: 0, 1LDSBuffer: 1, ScheduleLocalWrite: 0, LocalReadVectorWidth: 16.

• K = 32 validates.
• K = 96, 1000 and 1024 fail validation in tensilelite-client.
• In the generated assembly, the block between label_LoopBeginL and label_LoopEndL contains ds_store but no buffer_load.

Expected: the deferred global reads are issued after the local writes, as with ScheduleLocalWrite = 1.

No shipped logic uses ScheduleLocalWrite: 0, so shipped libraries are not affected. It does affect tuning and custom kernel configs.