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[atomicsabi64] Document release fence using ISHST+ISHLD barriers - #351

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stuij merged 2 commits into
ARM-software:mainfrom
Wilco1:atomic_fence
Nov 25, 2025
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stuij merged 2 commits into
ARM-software:mainfrom
Wilco1:atomic_fence

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@Wilco1

@Wilco1 Wilco1 commented Sep 15, 2025

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This allows more reordering than ISH.

This allows more reordering than ISH.
| ``atomic_thread_fence(release)`` | .. code-block:: none |
| | |
| ``atomic_thread_fence(acq_rel)`` | DMB ISH |
| | DMB ISHLD |

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To check my understanding, a combination of DMB ISHLD and DMB ISHST is a load-load, load-store and store-store barrier, but non store-load; but DMB ish is also a store-load barrier?

If so could be worth putting that or an explanation of why in the description/commit-message.

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I've added an explanation

Comment thread atomicsabi64/atomicsabi64.rst
reordering since the combination is not a store-load barrier.

@smithp35 smithp35 left a comment

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LGTM. Thanks for the update.

@Wilco1 Wilco1 changed the title Document release fence using ISHST+ISHLD barriers [atomicsabi64] Document release fence using ISHST+ISHLD barriers Sep 18, 2025
@stuij
stuij merged commit 36280d2 into ARM-software:main Nov 25, 2025
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3 participants