Renesas RH850-U2 LDL Instructions

1 Overview of LDL Instructions

1.1 Overview of LDL Instructions

● LDL.BU: Load linked byte unsigned
● LDL.HU: Load linked halfword unsigned
● LDL.W: Load linked word

2 LDL Instructions

2.1 LDL.BU Instruction

2.1.1 LDL.BU Instruction format and Operation

[Instruction format] 
LDL.BU [reg1], reg3 
 
[Operation] 
adr ← GR[reg1]
CheckException (MDP) 
GR[reg3] ← zero-extend (Load-memory (adr, Byte)) 
LLbit ← 1

2.1.2 LDL.BU Instruction Opcode

2.1.3 LDL.BU Instructions Description

Reads byte data from memory for an atomic read-modify-write, zero-extends it to word length, and stores the results in the general-purpose register reg3. Then, generates a link that corresponds to the address range including the specified address.
Subsequently, the link is lost if specific conditions are established before the STC.B instruction corresponding to the LDL.BU instruction is executed. If the STC.B instruction is executed with the link being lost, the result of the STC.B instruction indicates a failure.
If the STC.B instruction is executed with the link maintained, the result of the STC.B instruction is a success, in which case the link is also lost.
The LDL.BU and STC.B instructions may be used to carry out memory updates precisely in a multi-core system. The LDL.BU instruction and the STC.B instructions are intended always to be used in pair.

2.2 LDL.HU Instruction

2.2.1 LDL.HU Instruction format and Operation

[Instruction format] 
LDL.HU [reg1], reg3 
 
[Operation] 
adr ← GR[reg1]
CheckException (MAE) 
CheckException (MDP) 
GR[reg3] ← zero-extend (Load-memory (adr, Halfword)) 
LLbit ← 1

2.2.2 LDL.HU Instruction Opcode

2.2.3 LDL.HU Instructions Description

Reads halfword data from memory for an atomic read-modify-write, zero-extends it to word length, and stores the results in the general-purpose register reg3. Then, generates a link that corresponds to the address range including the specified address.
Subsequently, the link is lost if specific conditions are established before the STC.H instruction corresponding to the LDL.HU instruction is executed. If the STC.H instruction is executed with the link being lost, the result of the STC.H instruction indicates a failure.
If the STC.H instruction is executed with the link maintained, the result of the STC.H instruction is a success, in which case the link is also lost.
The LDL.HU and STC.H instructions may be used to carry out memory updates precisely in a multi-core system. The LDL.HU instruction and the STC.H instructions are intended always to be used in pair.

2.3 LDL.W Instruction

2.3.1 LDL.W Instruction format and Operation

[Instruction format] 
LDL.W [reg1], reg3 
 
[Operation] 
adr ← GR[reg1]Note 1
CheckException (MAE) 
CheckException (MDP) 
GR[reg3] ← Load-memory (adr, Word) 
LLbit ← 1

2.3.2 LDL.W Instruction Opcode

2.3.3 LDL.W Instructions Description

In order to perform an atomic read-modify-write operation, word data is read from the memory and stored in general-purpose register reg3. A link is then generated corresponding to the address range that includes the specified address.
Subsequently, if a specific condition is satisfied before an STC.W instruction is executed for this LDL.W instruction, the link will be deleted. If an STC.W instruction is executed after the link has been deleted, STC.W execution will fail.
If an STC.W instruction is executed while the link is still available, STC.W execution will succeed. The link is also deleted in this case.
The LDL.W and STC.W instructions can be used to accurately update the memory in a multi- core system. The LDL.W and STC.W instructions are intended always to be used in pair.