Buying a four-drive NVMe card or a second graphics card and plugging it into a spare PCIe x16 slot sounds simple, until the system boots and only one SSD shows up, or the second GPU reports as a PCIe x1 link running at a fraction of its rated speed. The missing piece is PCIe bifurcation, a BIOS-level setting that splits a single physical PCIe slot into multiple independent electrical links. Searches for “PCIe bifurcation” run around 720 a month in the US, according to DataForSEO keyword data pulled in October 2026, and the volume keeps climbing as more builders add Hyper M.2-style expansion cards and second GPUs to AM5 and Intel Arrow Lake Refresh systems for local AI inference.
This tutorial walks through enabling PCIe bifurcation correctly on a current-generation AMD X870E/X870/B850 or Intel Z890 motherboard, verifying the split actually took effect, and troubleshooting the handful of ways it silently fails. By the end you will have a working four-drive NVMe array or a dual-GPU rig with both cards running at their intended lane width, confirmed with real diagnostic output instead of guesswork.
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What PCIe Bifurcation Actually Does
A modern CPU exposes a fixed number of PCIe lanes, and those lanes are normally wired to a single x16 slot as one wide link. Bifurcation tells the motherboard firmware to treat that same physical slot as two, three, or four narrower, fully independent links instead of one wide one. The GPU slot on an AMD X870E board, for instance, is wired for either a single x16 link or two x8 links, according to AMD’s own AM5 chipset specification page. Nothing changes physically on the board; the traces and the slot are identical either way. What changes is how the chipset’s root complex addresses those lanes once the setting is applied in firmware.
That distinction matters because it is also the most common source of confusion. A board that lists “PCIe 5.0 x16” in its spec sheet is not automatically a board that supports x4/x4/x4/x4 bifurcation for a four-drive card. The chipset family sets the ceiling; the individual motherboard’s trace routing and BIOS menu decide what you can actually select. MSI’s own documentation for its X870E and X870 boards spells out four selectable PCIe Subsystem configurations: x16, x8+x8, x8+x4+x4, and x4+x4+x4+x4, but that list applies to the specific boards MSI documents it for, not to every board carrying the same chipset silicon.
Two use cases drive almost all PCIe bifurcation setup requests in 2026. The first is NVMe expansion: a passive four-drive card such as the ASUS Hyper M.2 or the ASRock Hyper Quad M.2 Card needs the host x16 slot split into four x4 links, because the card itself has no onboard switch logic, it just routes each physical M.2 socket to its share of the slot’s lanes. The second is multi-GPU builds for local large language model inference, where two consumer cards like an RTX 5080 or RTX 5090 each need a real x8 (or better) link rather than one running at x16 and the other starved down to x1 through a cheap riser.
Why PCIe Bifurcation Suddenly Matters Again in 2026
PCIe bifurcation is not a new feature. Server motherboards and workstation boards have exposed it for well over a decade, mostly for RAID controllers and SAS expansion cards that few consumer builders ever touched. What changed in 2026 is the audience. The arrival of local-first AI tooling, from Ollama-style self-hosted LLM runners to the broader wave of Windows and Linux AI PCs built around unified-memory platforms, pushed a much larger group of enthusiasts toward dual-GPU rigs they would never have considered two years ago. At the same time, PCIe 5.0 NVMe drives dropped in price enough that a four-drive array stopped being an enterprise-only proposition and became a realistic weekend project for a home NAS or a video editing workstation.
Both trends collide at the same bottleneck: a standard consumer motherboard only has one or two x16-length slots, and most builders assume that one slot means one device. Bifurcation is the feature that breaks that assumption, and it is also the feature that most consumer BIOS menus bury three submenus deep, under inconsistent naming, with almost no in-OS feedback when it fails silently. That combination, rising demand plus poor discoverability, is exactly why search interest in “PCIe bifurcation” has been climbing steadily through 2026 even though the underlying PCI Express specification feature itself has not changed.
Prerequisites and Versions
Confirm every item below before opening the case. Mismatched assumptions about chipset capability are the single biggest reason bifurcation setups fail on the first attempt.
| Requirement | Minimum spec / version | Notes |
|---|---|---|
| Motherboard chipset | AMD X870E, X870, or B850; Intel Z890 (select boards) | AMD lists B840 without CPU-lane bifurcation capability; verify B860 boards individually |
| BIOS/UEFI version | Latest vendor release as of Oct. 2026 | Gigabyte shipped BIOS F5c for the Z890 EAGLE WIFI7 PLUS in May 2026 and further updates through October |
| CPU | AMD Ryzen 9000/9000X3D series or Intel Core Ultra 200S/Arrow Lake Refresh | Lane count and bifurcation ceiling comes from the CPU-chipset link, not just the chipset model |
| Expansion card | ASUS Hyper M.2 (4-drive) or ASRock Hyper Quad M.2 Card | Passive cards; require host-side bifurcation to expose all drives |
| Power supply (dual GPU) | 1,000W+ for two RTX 5090s; 750W+ for RTX 5080/RX 9070 XT pairs | Keep 100-150W of headroom above measured peak load for transient spikes |
| Diagnostic tools | GPU-Z, HWiNFO, lspci (Linux) | Used in Step 9 to confirm the split actually applied |
| OS | Windows 11 24H2+ or a current Linux distro with kernel 6.x | UEFI boot mode required; disable legacy CSM |
One more thing worth checking before you buy anything: download the exact PDF manual for your motherboard model, not the chipset’s generic marketing page, and search it for the word “bifurcation.” If the word does not appear anywhere in the manual, the board likely does not expose the menu option even if the chipset theoretically supports it.
Step 1: Confirm Your Chipset’s Bifurcation Ceiling
Start with the chipset table below, pulled from AMD’s published AM5 chipset specifications and cross-checked against vendor BIOS documentation current as of October 2026. These numbers are the maximum the platform allows; your specific board may support less.
| Chipset | CPU graphics lanes | Storage lanes | Typical bifurcation modes |
|---|---|---|---|
| AMD X870E | x16 or 2×8 (PCIe 5.0) | x4 PCIe 5.0 + up to 4x GPP | x16, x8+x8, x8+x4+x4, x4+x4+x4+x4 (board-dependent) |
| AMD X870 | x16 or 2×8 (PCIe 5.0) | x4 PCIe 5.0 + up to 4x GPP | Same modes as X870E on boards that expose them |
| AMD B850 | x16 or 2×8 (PCIe 4.0) | x4 PCIe 5.0 | x8+x8 common; x4+x4+x4+x4 is optional and board-specific |
| AMD B840 | x16 only (PCIe 4.0) | x4 PCIe 4.0 | No CPU-lane bifurcation per AMD’s chipset spec |
| Intel Z890 | x16 or x8/x8 (select boards) | Varies by board | Check individual board manual; not guaranteed across the family |
| Intel B860 | Typically single CPU-connected slot | Varies by board | Often lacks a second CPU-connected slot for splitting |
If your board sits on B840 or a budget B860 model, stop here and reconsider your build before ordering a Hyper M.2 card or a second GPU. AMD’s own chipset documentation lists B840 without the CPU-lane bifurcation capability that X870E, X870, and B850 all carry, so no BIOS update will add a x4/x4/x4/x4 mode that the platform was never wired for.
Step 2: Verify PCIe Generation and Bandwidth Math
Before splitting a slot, know what each resulting link can actually deliver. A single PCIe 5.0 lane carries roughly 3.938 GB/s per direction after 128b/130b encoding overhead, so a PCIe 5.0 x4 link, the kind a bifurcated four-drive card produces, delivers around 15.75 GB/s per direction in theory. A PCIe 4.0 lane carries about 1.969 GB/s per direction, putting a PCIe 4.0 x4 link at roughly 7.88 GB/s, half the PCIe 5.0 figure.
| Link configuration | Generation | Theoretical bandwidth (per direction) | Typical use |
|---|---|---|---|
| x16 (unsplit) | PCIe 5.0 | ~63 GB/s | Single flagship GPU |
| x8 + x8 | PCIe 5.0 | ~31.5 GB/s each | Dual-GPU LLM inference rig |
| x4 + x4 + x4 + x4 | PCIe 5.0 | ~15.75 GB/s each | 4-drive Hyper M.2-style NVMe card |
| x4 + x4 + x4 + x4 | PCIe 4.0 | ~7.88 GB/s each | Budget 4-drive NVMe card on an older-gen link |
This is also where expectations about multi-GPU inference need a reality check. Two RTX 5090 or RTX 5080 cards running at x8/x8 instead of x16/x16 rarely bottleneck local LLM inference workloads in practice, because GPU memory capacity, inter-GPU communication overhead, and cooling tend to matter more than the raw difference between x8 and x16 PCIe 5.0 links for inference-only tasks. Do not buy a more expensive motherboard purely to chase x16/x16 if your real goal is two GPUs for inference rather than training.
Step 3: Check Your Board’s Exact Bifurcation Menu Name
Every BIOS vendor names this setting differently, and that inconsistency is the number one reason builders give up thinking their board “doesn’t support” bifurcation when the option is simply filed under an unexpected label. Based on current vendor documentation:
- ASUS: look for PCIEX16 Bifurcation, PCIe Bandwidth Bifurcation Configuration, or PCIe Link Configuration, usually under Advanced > PCI Subsystem Settings.
- MSI: filed under PCIe or PCI Subsystem Settings, with x16 / x8+x8 / x8+x4+x4 / x4+x4+x4+x4 listed as direct options on supported X870E and X870 boards.
- Gigabyte: model-specific naming, typically under Settings > PCIe Slot Configuration; check the board’s current BIOS changelog since Gigabyte has pushed active 2026 updates to boards like the Z890M GAMING X and the Z890 EAGLE WIFI7 PLUS.
- ASRock: look for a PCIe lane configuration or bifurcation entry near the primary PEG slot settings; presence of a physical “Hyper” card header does not by itself confirm which modes are available.
Write down the exact menu path for your board before you start, since you will be flipping back into this same submenu more than once while testing.
Step 4: Power Down, Install the Card or Second GPU, and Clear CMOS If Needed
Shut the system down fully and disconnect the PSU from mains power. Ground yourself before touching any card. Seat the Hyper M.2-style card (or second GPU) into the CPU-connected x16 slot, not a chipset-connected slot. This distinction matters more than most builders expect: a chipset-connected slot shares the chipset’s uplink bandwidth with USB, SATA, and networking controllers, and it frequently does not support the same bifurcation modes as a direct CPU-connected slot.
AMD’s own ROCm multi-GPU documentation is explicit on this point for GPU builds: “Only use PCIe slots connected by the CPU and to avoid PCIe slots connected via chipset.” The same logic applies to NVMe expansion cards. If you are not sure which slot is CPU-connected, the motherboard manual’s block diagram will show it, usually labeled as the primary PEG (PCI Express Graphics) slot.
If this is a used board or one that has had a BIOS update recently, consider clearing CMOS before your first boot attempt to rule out stale configuration data interfering with lane negotiation.
Step 5: Enter BIOS/UEFI and Locate the Bifurcation Setting
Power on and tap Delete or F2 (check your board’s manual; this varies) to enter firmware setup. Switch to Advanced Mode if your BIOS defaults to EZ Mode, since bifurcation controls are almost never exposed in the simplified view. Navigate to the menu path you identified in Step 3.
For a four-drive NVMe card, select x4+x4+x4+x4. For a dual-GPU build, select x8+x8. If your board only lists x16 and x8+x8 with no four-way option, your four-drive card will not work in that slot regardless of anything else you configure; that board simply was not wired for a four-way split.
Step 6: Enable Above 4G Decoding
Find Above 4G Decoding (sometimes listed as Above 4G MMIO) under the same PCI Subsystem or Advanced menu and set it to Enabled. This setting gives PCIe devices access to memory address space above the 4GB boundary, which becomes necessary once you have multiple GPUs or several PCIe 5.0 NVMe controllers all requesting address space simultaneously. It commonly appears right next to Resizable BAR in the BIOS, but the two are not the same setting, Resizable BAR controls how a CPU addresses GPU VRAM and is not itself a bifurcation requirement, though multi-GPU builds typically want both enabled.
BIOS path example (ASUS):
Advanced > PCI Subsystem Settings > Above 4G Decoding = Enabled
Advanced > PCI Subsystem Settings > Re-Size BAR Support = Enabled (dual-GPU builds only)Step 7: Decide Whether You Need IOMMU
IOMMU (listed as SVM Mode plus IOMMU on AMD boards, or VT-d on Intel boards) is not required simply to make a passive four-drive NVMe card enumerate correctly. Leave it disabled unless you specifically need PCI device passthrough, virtualization with dedicated device isolation, or you are running a hypervisor that assigns individual NVMe controllers or GPUs to separate virtual machines. Enabling it unnecessarily adds complexity without benefit for a straight bare-metal NVMe array or dual-GPU inference box.
Step 8: Save, Exit, and Confirm UEFI Boot Mode
Save changes (typically F10) and reboot. While you are in the boot menu, confirm the system is using UEFI boot rather than legacy CSM. Mixed CSM/UEFI configurations are a known source of inconsistent device enumeration on boards with multiple GPUs or several NVMe controllers, since some firmware implementations re-order devices differently between the two modes. If CSM is still enabled from an older OS install, disable it now.
Step 9: Verify the Split Actually Applied
This is the step most tutorials skip, and it is the one that actually tells you whether your changes did anything. Boot into your OS and check each device independently rather than trusting that “it detected everything” means the lanes are correct.
On Windows with GPU-Z: open GPU-Z, check the “Bus Interface” field for each GPU, and run GPU-Z’s built-in render test. The bus width reported should match what you selected (x8 for a dual-GPU x8+x8 split, not x16 or x1).
On Windows with HWiNFO: open the sensor tree, expand each GPU entry, and check the PCIe link width and link speed fields live. For a four-drive NVMe card, HWiNFO’s storage section should show four separate NVMe controllers, each with its own link width, rather than one controller and three missing drives.
On Linux: run the following and inspect LnkCap (capability) against LnkSta (actual negotiated status) for each device:
sudo lspci -vv | grep -A 30 "Non-Volatile memory controller"
# Look for lines like:
# LnkCap: Port #0, Speed 32GT/s, Width x4
# LnkSta: Speed 32GT/s (ok), Width x4 (ok)
nvme list
# Confirms how many NVMe drives the OS actually enumerates
fio --name=bifurcation-test --filename=/dev/nvme1n1 --rw=read --bs=1M --size=2G --direct=1 --numjobs=1If LnkSta reports a narrower width than LnkCap (for example, Width x4 capable but x1 negotiated), the physical link trained down, usually meaning a cabling, riser, or seating issue rather than a BIOS misconfiguration. If only one of four expected NVMe controllers appears at all, the bifurcation setting did not take effect and you need to revisit Step 5.
Step 10: Benchmark the Real-World Result
Confirming link width is necessary but not sufficient, since a correctly trained link can still underperform if drivers, firmware, or thermal throttling get in the way. Run a short sequential and random I/O test on each drive independently using fio (Linux) or diskspd (Windows), then run the same test with all four drives loaded simultaneously to confirm aggregate throughput scales roughly in line with four independent x4 links rather than collapsing toward the bandwidth of one shared link.
For dual-GPU inference setups, load your actual inference workload (for example, a quantized model split across both cards with your inference framework‘s tensor-parallel or pipeline-parallel mode) and watch GPU utilization on both cards. If one GPU consistently sits near 100% while the other idles, the bottleneck is more likely software configuration (model splitting) than the PCIe link itself.
Step 11: Address Thermal and Power Considerations
Four PCIe 5.0 NVMe drives packed onto one card generate meaningfully more heat than a single boot drive, especially under sustained sequential writes. Use the card’s included heatsink, and make sure the slot sits in a chassis zone with active airflow; a four-drive card mounted directly beneath a hot GPU with no case fan nearby will throttle under load regardless of how correctly the lanes are configured.
For dual-GPU builds, recalculate your power budget rather than assuming your existing PSU has headroom. A system running two RTX 5090 cards benefits from 1,000W or more, while a pairing of an RTX 5080 or RX 9070 XT per card is more commonly cited around the 750W mark; in both cases, keep 100 to 150W of spare capacity above your measured peak system draw to absorb transient power spikes that a card’s rated TDP figure does not fully capture.
Step 12: Document Your Working Configuration
Once everything verifies correctly, record the exact BIOS version, the exact menu path, and the selected mode (x8+x8 or x4+x4+x4+x4) somewhere outside the machine. BIOS updates occasionally reset custom PCIe subsystem settings to default, and without a written record you will be re-deriving the correct configuration from scratch after every firmware update. This single habit saves more troubleshooting time than any other step in this guide.
Complete Working Project: A 4-Drive NVMe Array on an X870E Board
Putting the full sequence together for the most common request, a four-drive NVMe array built around an X870E motherboard and a passive Hyper M.2-style card:
- Confirm the board is X870E (not B850 or lower) and the manual explicitly lists x4+x4+x4+x4 as a supported mode for the primary PEG slot.
- Update to the latest BIOS from the vendor’s support page before making any changes.
- Seat the four-drive card in the CPU-connected x16 slot, install all four NVMe drives onto the card.
- In BIOS, set the PCIe subsystem bifurcation mode to x4+x4+x4+x4, enable Above 4G Decoding, save and exit.
- Boot into the OS, confirm UEFI mode is active, and run lspci -vv (or open HWiNFO) to confirm four independent NVMe controllers each training at x4.
- Run fio or diskspd on each drive individually, then all four simultaneously, to confirm aggregate throughput scales as expected.
- Configure the array in your OS (Storage Spaces, mdadm, ZFS, or your NAS software of choice) once all four drives confirm correct link width.
- Write down the final BIOS version and settings for future reference.
The same sequence applies to a dual-GPU inference build, substituting x8+x8 for x4+x4+x4+x4 in step four and GPU-Z plus your inference framework’s utilization monitor for the drive-focused verification in steps five and six.
Variant: Dual-GPU Build for Local LLM Inference
For a dual-GPU inference rig, the same twelve-step sequence applies with a different end goal. Start from an X870E board, since AMD documents it with the most consistent two-slot, CPU-connected x8/x8 graphics wiring across board partners. Install both GPUs in the two CPU-connected slots identified in your board’s block diagram, not a secondary chipset-linked slot, since AMD’s own ROCm documentation specifically warns against chipset-connected slots for multi-GPU work. Set the BIOS bifurcation mode to x8+x8, enable both Above 4G Decoding and Resizable BAR, and confirm UEFI boot mode exactly as described in Steps 6 through 8.
Verification looks different for a GPU pair than for an NVMe array. Open GPU-Z for each card individually and confirm the Bus Interface field reports x8, not x16 (which would mean the second card isn’t actually sharing the link as expected) and not x1 or x4 (which would mean the split failed or a card is seated in the wrong slot). Load your inference framework of choice, split a quantized model across both cards using its tensor-parallel or pipeline-parallel configuration, and watch utilization on both GPUs during a real prompt. Balanced utilization across both cards, rather than one pegged at 100% while the other idles, confirms the software-side model split is working correctly on top of your now-verified hardware configuration.
Budget your power supply for this variant before you buy anything else. Two RTX 5090 cards in one chassis is a 1,000W-plus build once you add CPU, storage, and fans, and a pair of RTX 5080 or RX 9070 XT cards still comfortably clears 750W. Keeping 100 to 150W of headroom above your actual measured peak draw matters more here than on a single-GPU build, since two flagship cards drawing simultaneous transient spikes under a heavy inference burst is a different load profile than one card alone.
5 Common Pitfalls That Break Bifurcation Setups
- Assuming chipset support equals board support. AMD’s chipset specification lists maximum platform capability, not a guarantee that your specific motherboard model wired the traces for every listed mode. Always check the individual board manual.
- Using a chipset-connected slot instead of a CPU-connected one. A chipset-linked slot shares bandwidth with USB, SATA, and networking, and often cannot run the bifurcation mode you need.
- Populating an M.2 socket that shares lanes with your bifurcated slot. On many boards, filling certain onboard M.2 slots silently drops the primary PEG slot from x16 to x8, or disables a secondary slot entirely, long before you even get to the Hyper M.2 card.
- Buying a passive card expecting switch-based behavior. A passive Hyper M.2-style card has no onboard PCIe switch; without correct host bifurcation it will expose only one of its four drives. A PCIe switch card costs more but can work in an unsplit x16 slot, confirm which architecture you’re buying before assuming either will “just work.”
- Skipping verification and trusting Device Manager. Windows Device Manager showing four drives does not confirm they are each running at x4; only GPU-Z, HWiNFO, or lspci’s LnkSta field confirms actual negotiated link width.
Troubleshooting: 8+ Issues and Fixes
| Symptom | Likely cause | Fix |
|---|---|---|
| Only one of four NVMe drives detected | Bifurcation mode not applied, or applied to the wrong slot | Re-enter BIOS, confirm x4+x4+x4+x4 is selected for the exact slot the card occupies |
| Second GPU shows as x1 in GPU-Z | Card seated in a chipset-connected slot, or riser/cable fault | Move the card to the CPU-connected PEG slot per the motherboard block diagram; reseat cables |
| Bifurcation option grayed out or missing entirely | Board model does not support the mode, or BIOS is outdated | Update BIOS first; if still missing, the board was never wired for that split |
| System won’t POST after enabling x4+x4+x4+x4 | Above 4G Decoding not enabled, or stale CMOS data | Clear CMOS, re-enable the bifurcation setting, then enable Above 4G Decoding before saving |
| Primary GPU drops from x16 to x8 unexpectedly | Filling certain onboard M.2 slots shares lanes with the primary PEG slot | Check the manual’s lane-sharing table; move SSDs to a non-shared M.2 slot |
| lspci shows correct LnkCap but lower LnkSta | Link trained down due to a signal integrity or seating issue | Reseat the card, check riser cable quality, try a different physical slot if available |
| Four drives detected but aggregate throughput far below expected | Drives sharing a link that isn’t actually four independent x4 paths | Re-run lspci -vv per drive; confirm each reports its own LnkSta rather than a shared value |
| Dual GPUs detected correctly but inference throughput is uneven | Software-level model splitting, not a PCIe issue | Check your inference framework’s tensor/pipeline-parallel configuration rather than the BIOS |
| Settings revert after a BIOS update | Firmware updates often reset PCIe subsystem settings to default | Keep a written record of your configuration (Step 12) and reapply after each update |
Advanced Tips for Multi-GPU and NVMe Builds
For builders chasing maximum reliability on NVMe arrays, prefer a card and board combination where the manual explicitly states the lane-sharing table rather than inferring it from a block diagram alone; this is listed as the most dependable purchasing workflow in current AM5 chipset guidance. For dual-GPU inference rigs specifically, AMD’s ROCm documentation recommends a 1:1 ratio between the number of CPU-connected x16-capable slots and the number of GPUs installed, which in practice steers most builders toward X870E over X870 or B850 once a second GPU enters the picture, since X870E is the AM5 chipset AMD documents with the most consistent two-slot CPU-graphics wiring across board partners.
If you are building for virtualization alongside bifurcation, for example assigning individual NVMe controllers or GPUs to separate VMs, enable IOMMU (SVM + IOMMU on AMD, VT-d on Intel) at this point rather than earlier in the process, since troubleshooting device passthrough is considerably easier once you’ve already confirmed bare-metal link widths are correct without it.
Bifurcation also shows up outside consumer desktops. NVIDIA’s own BlueField-3 DPU documentation describes splitting a single x16 interface into four x4 links to connect multiple PCIe endpoints including NVMe SSDs, the identical underlying mechanism scaled to a different form factor. Understanding that this is a standard PCIe Base Specification feature, not a desktop-motherboard gimmick, helps explain why the BIOS terminology and verification tools (lspci’s LnkCap/LnkSta fields) are consistent whether you’re configuring a $300 consumer board or a data-center DPU.
PCIe Bifurcation vs. PCIe Switch Cards: Which Should You Buy
Not every four-drive NVMe card relies on host bifurcation. Passive cards, the ASUS Hyper M.2 and ASRock Hyper Quad M.2 Card among them, route each M.2 socket directly to a quarter of the host slot’s lanes and need the motherboard to supply four genuine x4 links. Switch-based cards instead carry an onboard PCIe switch chip that fans a single x16 (or x8) host connection out to four drives internally, which means they can work in a slot that has not been bifurcated at all, at the cost of a notably higher price and, in some implementations, added latency.
| Factor | Passive (bifurcation-dependent) card | Switch-based card |
|---|---|---|
| Motherboard requirement | Must support x4+x4+x4+x4 bifurcation | Works in most unsplit x16 slots |
| Typical cost | Lower | Higher, due to onboard switch silicon |
| Latency | None added (direct lane routing) | Slightly higher, switch adds a hop |
| Best fit | Builders who already confirmed board-level bifurcation support | Builders on boards without bifurcation, or wanting slot flexibility |
If your board’s manual already confirms x4+x4+x4+x4 support, a passive card is the more cost-effective choice. If you are not confident about your board’s bifurcation support, or you want to move the card between systems with different motherboards, a switch-based card trades extra cost for far fewer compatibility questions.
AMD AM5 vs. Intel Z890: Which Platform Makes Bifurcation Easier
If you are shopping for a motherboard specifically to run a bifurcated four-drive card or a dual-GPU rig, the platform choice is not neutral. AMD publishes its AM5 chipset bifurcation ceilings openly, and multiple board partners, including MSI, document the exact selectable split modes (x16, x8+x8, x8+x4+x4, x4+x4+x4+x4) in their own support pages rather than leaving it to third-party forum testing. That level of vendor documentation makes AM5 X870E and X870 boards considerably easier to shop for with confidence, because you can often confirm bifurcation support from the manufacturer’s own site before ordering anything.
Intel’s current Z890 platform is less consistently documented on this specific point. ASUS lists up to two PCIe 5.0 expansion slots on its Z890 boards, but whether a given model supports a four-way x4+x4+x4+x4 split, rather than just a simpler x8/x8 GPU split, is something you will more often need to confirm by downloading the individual board manual rather than reading the chipset’s marketing page. Gigabyte and other partners have shipped active 2026 BIOS updates to Z890-series boards, which is a good sign that firmware support is maturing, but it also means the exact feature set can shift between BIOS versions on the same model.
The practical takeaway: if a four-drive NVMe card or a dual-GPU inference rig is the primary goal and you have not already committed to a platform, AM5 X870E currently has the more consistently documented bifurcation story across board partners. If you are locked into Intel for other reasons, CPU performance, platform longevity, or an existing Z890 board, just budget extra time to read the specific board’s manual before buying an expansion card, since the chipset name alone tells you less on this platform than it does on AM5.
Frequently Asked Questions
Does every PCIe 5.0 motherboard support PCIe bifurcation?
No. Chipset specifications describe the maximum lane configuration the platform allows, but individual motherboard models decide, through trace routing and BIOS firmware, which specific split modes are actually exposed. Always check your exact model’s manual rather than assuming based on the chipset name alone.
Can I use PCIe bifurcation on a B840 motherboard?
AMD’s own chipset specification lists B840 with only a single x16 PCIe 4.0 graphics link and no CPU-lane bifurcation capability, unlike X870E, X870, and B850. A B840 board is not a suitable choice for a four-drive NVMe card or a dual-GPU build.
Do I need Above 4G Decoding for bifurcation to work?
Yes, for multi-GPU builds and setups with several PCIe 5.0 NVMe controllers requesting memory address space simultaneously, Above 4G Decoding should be enabled. It is commonly found alongside Resizable BAR in the BIOS, but the two settings control different things.
Is IOMMU required for a basic four-drive NVMe setup?
No. IOMMU (or VT-d on Intel) is primarily needed for PCI device passthrough and virtualization workflows where individual devices are isolated to separate virtual machines. A straightforward bare-metal NVMe array does not require it.
How do I confirm bifurcation actually worked after changing the BIOS setting?
Check the negotiated link width independently for each device. On Windows, use GPU-Z’s Bus Interface field or HWiNFO’s PCIe link width readout. On Linux, run lspci -vv and compare the LnkCap (capability) and LnkSta (actual negotiated status) fields for each device.
Will running two GPUs at x8/x8 instead of x16/x16 hurt local LLM inference performance?
In most inference-only workloads, the difference between x8 and x16 PCIe 5.0 matters less than GPU memory capacity, cooling, and how your inference framework splits the model across cards. The PCIe link width becomes a bigger factor in training workloads with heavy inter-GPU communication than in straightforward inference.
Why did my four NVMe drives disappear after a BIOS update?
Firmware updates frequently reset PCIe subsystem settings, including bifurcation mode, back to the board’s default. Re-enter the BIOS menu and reselect your previous configuration; this is why documenting your exact settings in advance (see Step 12) saves significant troubleshooting time.
What’s the difference between a passive bifurcation card and a PCIe switch card?
A passive card, like the ASUS Hyper M.2 or ASRock Hyper Quad M.2 Card, has no onboard switching logic and requires the motherboard to supply genuinely independent x4 links through bifurcation. A switch-based card contains its own PCIe switch chip and can function in a standard, unsplit x16 slot, at a higher price and with a small added-latency hop.
