AMD closed a two-day event in San Francisco on July 23, 2026 by handing the server chip industry its clearest signal yet of who is setting the pace in the data center. At Moscone West, CEO Dr. Lisa Su walked the Advancing AI 2026 crowd through the formal debut of EPYC “Venice,” now officially branded the EPYC 9006 series and marketed as AMD’s first Zen 6 server processor and the first x86 chip built in volume on a 2-nanometer-class process, a chip AMD’s own investor relations team says first taped out on TSMC’s 2nm N2 node back in April 2025. The launch lands at a moment when AMD’s EPYC line already holds a record 46.2% of x86 server CPU revenue, according to Mercury Research, up from 39.5% a year earlier.
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AMD’s Zen 6 Era Begins: EPYC Venice Launches at Advancing AI 2026
The event, held July 22-23 at the Moscone Center, doubled as AMD’s broadest data center pitch of the year, pairing Venice with new Instinct MI450-series AI accelerators and a rack-scale system called Helios. AMD CTO Mark Papermaster had teed up the announcement weeks earlier at the RAISE Summit in Paris, and confirmed it again on stage: “So, at our Advancing AI event on July 22nd and 23rd, we’re rolling out this new generation,” he said. (source)
For enterprise buyers and cloud architects, the launch reopens a question that looked settled as recently as 2020: whether Intel or AMD controls the default choice for new server capacity. The market share numbers below suggest that question now has a very different answer than it did five years ago, and the launch itself gives buyers a concrete new option to evaluate starting this quarter.
Venice Rollout Timeline: From Teaser to Production Ramp
Venice’s path from announcement to shipping silicon has moved fast by server-CPU standards, and it started earlier than the July keynote suggested. AMD’s own investor relations disclosures show the company announced on May 21, 2026 that Venice’s 2nm production ramp was underway at TSMC’s Taiwan fabs, with AMD flagging future ramp capacity planned for its Arizona facilities as well, two months before Papermaster teased the rollout at the RAISE Summit in Paris and confirmed the formal debut on stage at Advancing AI. AMD then followed through on August 5, 2026 by confirming that Venice had entered full production ramp on TSMC’s 2nm process, a milestone the company framed as proof its Q3 2026 shipping timeline is holding. As of this writing in August 2026, that puts Venice roughly a month past its formal debut and squarely inside the production window that determines whether systems actually reach customer racks on schedule.
- Weeks before launch: Papermaster previews the Zen 6 rollout at the RAISE Summit in Paris.
- July 22-23, 2026: EPYC Venice formally launches at AMD’s Advancing AI event in San Francisco.
- August 5, 2026: AMD confirms Venice has entered production ramp on TSMC’s 2nm (N2-class) process.
- Q3 2026 (target): Venice systems begin shipping to customers, with Helios and MI450-series-paired configurations dependent on HBM4 allocation.
Inside EPYC Venice: 256 Cores, 2nm and a New Playbook
Venice’s headline spec is scale. AMD’s flagship Zen 6 server chip, topped by the EPYC 9996 SKU, packs up to 256 cores and 512 threads, arranged across eight compute dies and two I/O dies, a 33% jump past the 192-core ceiling of last year’s Turin generation, per Tom’s Hardware. It pairs with 16-channel DDR5 memory and 128 lanes of PCIe Gen 6 connectivity on the SP7 socket, a first for a shipping server CPU, which StorageReview measured at up to 1.6 TB/s of aggregate memory bandwidth on the flagship part, up from roughly 614 GB/s on the prior generation and a roughly 18x throughput gain over AMD’s first EPYC chips in 2017, with SP7 TDPs scaling as high as 600W to support that added core and I/O density, and boost clocks on the flagship EPYC 9996 reaching 4.1GHz, according to a September 2026 spec breakdown from The Register. (source) Multiple outlets, including ServeTheHome, report a new SP7 platform with a smaller SP8 footprint for entry-level parts, while TweakTown notes some EPYC 9006-series SKUs pair those 256 Zen 6c cores with up to 1,152MB of 3D V-Cache; as of September 2026, StorageReview counts 31 SKUs across the full EPYC 9006 stack, priced from roughly $700 for the entry-level EPYC 9016 up to $14,904 for the flagship EPYC 9996, with TechPowerUp reporting that the initial SP7-socket Venice systems are slated to ship in Q4 2026 while the smaller SP8 platform for those entry parts isn’t expected to follow until the first half of 2027.
The manufacturing shift matters as much as the core count. Moving to TSMC’s N2-class node lets AMD pack more compute into the same power envelope, and power, not floor space, is usually the real ceiling on how much compute a data center operator can deploy per rack. ServeTheHome’s early coverage of the platform put the generational jump at 1.3x thread density and 1.7x performance over the prior generation, echoing the roughly 70% performance boost AMD itself had already reaffirmed for the up-to-256-core Venice lineup on its Q3 2025 earnings call, as reported by TweakTown. (source) AMD’s own July 2026 blog post on the EPYC 9006 series confirms those figures officially, listing up to 256 cores, 512 threads and 16 DDR5 memory channels for the standard Venice lineup, while VRLA Tech separately reports the flagship EPYC 9996 part carries 1,024MB of L3 cache alongside its 256 cores and 512 threads. AMD confirmed on August 5, 2026 that it had begun the production ramp of Venice on TSMC’s 2nm process, calling the milestone a proof point for the AMD-TSMC 2nm collaboration and a concrete signal that the chip’s Q3 2026 shipping timeline is holding. AMD has since put numbers behind that performance edge: a September 2026 AMD benchmark disclosure claimed the EPYC 9996 delivers 2.24 times the throughput of Nvidia’s competing Vera platform, while Tom’s Hardware separately reported, also in September 2026, AMD’s claim that a Venice chip runs roughly 20% faster per core than Nvidia’s Vera chip. Papermaster described the standard Venice part as “optimized for standalone x86 traditional workloads,” a distinction that separates it from AMD’s accelerator-attached parts built for AI training clusters. (source)
Venice-X Brings 3D V-Cache to the Server Line in 2027
AMD also confirmed a second Zen 6 server variant built for high-performance computing customers. Venice-X, due in the second half of 2027, pairs a smaller 96-core count with 1,152MB of 3D V-Cache and boost clocks up to 5.15GHz, trading raw core density for the cache-heavy performance that workloads like computational fluid dynamics and chip-design simulation depend on. (source) The split mirrors what AMD already does on the desktop with its X3D gaming chips, applied here to a market segment where cache size can matter more than core count.
Record 46.2%: Breaking Down AMD’s Server Market Share Surge
The market share data is the part of this story with the clearest paper trail. Mercury Research’s Q1 2026 figures put AMD’s EPYC line at 46.2% of x86 server CPU revenue, a fourth consecutive quarterly record and a jump of 6.7 percentage points from the 39.5% AMD held a year earlier. (source) AMD has pointed to a $2 trillion total compute TAM by 2030 and has said it aims to capture up to 50% of the server market share. (source)
| Period | Metric | AMD Share | Source |
|---|---|---|---|
| 2017 | Overall server CPU market (all vendors) | Under 1% | AMD roadmap disclosures via Tom’s Hardware |
| Mid-2025 | x86 server CPU revenue (Turin generation) | ~40% | Industry/company reporting |
| Late 2025 | Overall server CPU market (all vendors) | ~29% | Tom’s Hardware analysis |
| Q1 2025 | x86 server CPU revenue | 39.5% | Mercury Research |
| Q1 2026 | x86 server CPU revenue (record) | 46.2% | Mercury Research |
| Q1 2026 | x86 server CPU unit share | 33.2% | Mercury Research |
| AMD’s stated target | x86 server CPU revenue (goal, undated) | 50%+ | AMD, Advancing AI 2026 |
Look closely at the two AMD figures from the same Mercury Research report and a second story appears. AMD’s revenue share (46.2%) runs well ahead of its unit share (33.2%), meaning AMD sells proportionally fewer chips at much higher average prices. That gap is a function of mix: hyperscalers buying top-bin 256-core Venice and 192-core Turin parts pull revenue share up faster than unit share, while lower-core-count chips still move in higher volumes elsewhere in the market. Put differently, AMD is winning the high end of the market faster than it is winning the market overall.
From Sub-1% to Market Leader: A Decade of AMD’s Data Center Comeback
Context helps explain why Wall Street and IT buyers are paying attention now. AMD supplied less than 1% of server CPUs in 2017, the year it launched the first EPYC chips, codenamed Naples, to challenge Intel’s decade-long lock on the data center. (source) By late 2025, AMD’s share of the broader server CPU market, a measure that includes Arm-based competition, had climbed to roughly 29%, while its x86-only revenue share reached about 40% around the same period on the strength of the Turin generation, with Oracle, Google Cloud, Microsoft Azure and Amazon EC2 all running Turin at scale.
Venice extends a run that started with Rome and Milan in the early 2020s and continued through Genoa and Turin, with each generation narrowing the gap against Intel on raw performance and, increasingly, on power efficiency per core. What makes the current stretch different is speed. AMD needed most of a decade to go from irrelevant to competitive, and less than three years to go from competitive to the outright revenue leader.
Helios and MI450: AMD’s Rack-Scale Answer to Nvidia
Venice was only half of what AMD showed in San Francisco. The company also introduced its Instinct MI450 and MI455X AI accelerators alongside Helios, described as AMD’s first fully integrated rack-scale AI system, combining Venice CPUs, MI-series GPUs and AMD networking gear into a single deployable unit. Industry coverage frames Helios as AMD’s direct answer to Nvidia’s Vera Rubin platform, Nvidia’s own next-generation rack-scale AI system. (source) For more on how AMD’s accelerators stack up against Nvidia’s current generation, see our AMD MI350P vs. Nvidia H200 comparison.
AMD is already previewing what comes after. Its public roadmap points to Instinct MI500-series accelerators built on CDNA 6 architecture in 2027, deployed in what the company calls a 256-way MegaPod configuration, a sign AMD intends to keep pace with Nvidia’s roughly annual accelerator cadence rather than the two-year refresh cycle that used to define the GPU business. (source)
The HBM4 Bottleneck: Why Supply, Not Chip Design, Sets the Pace
The constraint on how fast any of this reaches customers is not silicon design. It is memory. Reporting around the Venice launch indicates that HBM4, the high-bandwidth memory that feeds Helios racks and MI455X accelerators, is largely allocated to hyperscale customers through the rest of 2026, and some independent analysts believe MI455X shipments are themselves capped by how much HBM4 AMD can secure. (source) That squeeze sits alongside a broader memory crunch already pushing up DRAM and NAND pricing across the PC and server markets this year, a trend we covered when DRAM prices hit record highs earlier in 2026.
Nvidia and SK Hynix’s memory supply agreement, reported earlier this year at roughly $500 billion, underlines how central HBM4 has become to the entire AI hardware stack, not just to Nvidia’s own GPUs. Our coverage of that deal found the same dynamic playing out industry-wide: whoever locks up memory supply first controls how fast its AI hardware roadmap actually ships, regardless of how strong the chip design looks on paper.
Who’s Buying: Meta, Oracle, OpenAI, Microsoft and the DOE
AMD did not launch Venice into a vacuum. The company points to gigawatt-scale compute commitments from Meta and OpenAI, a confirmed MI450-series partnership with Oracle, and a role for both EPYC Venice and Instinct MI430X GPUs in a next-generation supercomputer selected by the U.S. Department of Energy. (source) Microsoft is also named among AMD’s committed partners for the current AI hardware stack, though public deal terms remain limited.
Those commitments build on a customer base Turin already established. Oracle, Google Cloud, Microsoft Azure and Amazon EC2 were all running EPYC Turin at scale before Venice arrived, giving AMD a validated path into the same accounts for the newer chip instead of a cold sales cycle. That existing footprint, more than any single spec on a slide, is why analysts treat AMD’s 46.2% share as durable rather than a one-quarter spike tied to a single launch event.
Intel’s Answer: Clearwater Forest Ships, Diamond Rapids Doesn’t (Yet)
Intel has not stood still. Its current Xeon 6 lineup includes Granite Rapids, a performance-core chip built on Intel 3 with up to 128 cores and support for DDR5-6400 memory and 8,000 MT/s MRDIMMs, and Sierra Forest, an efficiency-core design that tops out at 144 cores on the same process. (source) More recently, Intel shipped Clearwater Forest, a Xeon 6+ efficiency-core chip built on its 18A process with up to 288 cores, giving Intel a genuine core-count answer to Venice even as AMD leads on memory bandwidth and per-core performance. (source)
| CPU | Vendor | Process Node | Max Cores | Memory / I-O | Status |
|---|---|---|---|---|---|
| EPYC Venice (Zen 6) | AMD | TSMC N2 (2nm-class) | 256 | 16-channel DDR5, PCIe 6.0 | Launched July 22-23, 2026; production ramp underway; systems ship Q3 2026 |
| EPYC Turin (Zen 5) | AMD | TSMC 3nm/4nm-class (SKU-dependent) | 192 | DDR5, SP5 platform, PCIe 5.0 | Shipping since October 2024 |
| Xeon 6 Granite Rapids | Intel | Intel 3 | 128 | DDR5-6400 / MRDIMM 8000, PCIe 5.0 | Shipping since September 2024 |
| Xeon 6E Sierra Forest | Intel | Intel 3 | 144 | DDR5-6400, PCIe 5.0 | Shipping since June 2024 |
| Xeon 6+ Clearwater Forest | Intel | Intel 18A | 288 | DDR5, PCIe 5.0 | Launched mid-2026 |
| Diamond Rapids (“Xeon 7”) | Intel | Unconfirmed | Undisclosed | Undisclosed | No confirmed launch year; media reports point to 2027 |
What Intel has not shipped is a direct performance-core rival to Venice. Diamond Rapids, referred to in some coverage as “Xeon 7,” remains the more direct architectural competitor, and Intel has not publicly confirmed a launch year, process node or core count for it. Industry coverage has floated mid-2027 as the earliest realistic date for a true head-to-head part. (source) Until then, AMD effectively has the high end of the performance-core x86 market to itself.
The Number Intel Doesn’t Advertise
Read Mercury Research’s two AMD figures side by side and Intel’s actual position looks stronger than the 46.2% headline suggests. If AMD holds 33.2% of x86 server CPU units against 46.2% of revenue, the arithmetic implies Intel still ships roughly two-thirds of the x86 server chips sold each quarter, even while collecting a shrinking slice of the revenue. Intel remains the volume default across mainstream enterprise racks. It is losing the premium, AI-adjacent, high-core-count tier where the industry’s growth and margin now concentrate.
Where Arm Fits Into the Picture
The x86 fight is not the only one AMD has to win. Arm-based server chips, including AWS’s Graviton line, Google’s Axion and Nvidia’s own Grace CPU, keep taking share inside the hyperscalers that design their own silicon, even as AMD and Intel dominate the merchant market that everyone else buys from. Our AWS Graviton vs. Intel/AMD comparison found Graviton instances running roughly 45% cheaper on a price-performance basis for compatible workloads, a gap that keeps Arm relevant for cloud-native applications even as EPYC wins the broader x86 server socket count.
That split, AMD and Intel fighting over merchant x86 silicon while hyperscalers quietly build Arm chips for their own internal fleets, is likely to define data center CPU competition for the rest of the decade more than any single launch event, including this one.
Wall Street’s Read: AMD’s Valuation and the Numbers That Matter
AMD arrived at Advancing AI 2026 already priced for growth. Shares traded near $539 in mid-July, days ahead of the event, with the company’s market capitalization approaching $900 billion, according to a TechTimes analysis published July 13. (source) That same analysis floated a roughly 25% run toward a $1 trillion valuation if Venice and Helios land as promised, though that framing reflects one analyst’s pre-event expectations rather than a confirmed outcome.
The fundamentals behind that optimism are concrete, even where the stock-price forecasting is not. AMD’s Q1 2026 revenue reached $10.3 billion, up 38% year over year, with the Data Center segment alone contributing $5.8 billion, up 57%. (source) Those figures predate Venice’s commercial availability, which means the real test of whether the launch translates into revenue will show up once Q3 2026 shipments actually land in customers’ racks.
What Enterprise Buyers Should Do Right Now
For IT teams sizing new server purchases in the back half of 2026, the practical guidance splits by workload. Teams buying general-purpose compute at the highest end of the core-count spectrum have a genuine reason to put Venice through procurement evaluation once Q3 2026 shipments begin, particularly for consolidation projects where fewer, denser servers cut rack and power costs. Teams with existing Turin or Xeon 6 deployments have less urgency, since both platforms remain fully current and a mid-cycle swap rarely pencils out against a same-generation capacity expansion.
AMD’s confirmation of a production ramp start in early August 2026 removes some of the timeline risk that typically shadows a first-generation launch, but buyers should still confirm OEM-specific delivery windows before finalizing budgets. The bigger near-term risk is availability, not architecture. With HBM4 supply constrained through the rest of 2026, buyers chasing MI450-series accelerators or Helios rack allocation should expect lead times well beyond typical CPU-only orders, and should start capacity conversations with AMD or its OEM partners now rather than after budget approval.
Expert Take: What AMD’s Own Executives Are Saying
AMD’s own leadership has been consistent about the stakes of this launch. At Advancing AI, CTO Mark Papermaster confirmed the rollout directly from the stage: “So, at our Advancing AI event on July 22nd and 23rd, we’re rolling out this new generation,” he told the audience. (source)
Papermaster also drew a clear line between Venice’s target workloads and AMD’s accelerator-attached parts, describing the standard chip as a processor “optimized for standalone x86 traditional workloads.” (source) That framing matters for buyers deciding between a CPU-only Venice deployment and a full Helios rack, since AMD is explicitly positioning them as different products for different jobs rather than one platform for everything. Independent technical coverage from ServeTheHome corroborated the underlying process shift, reporting that AMD confirmed its Zen 6 and Zen 6c cores are built on TSMC’s 2nm node, specs both The Register and EENews Europe corroborated in September 2026 by listing the EPYC 9996 flagship’s 1,024MB of L3 cache, 600W TDP and 4.1GHz boost clock alongside its 128 PCIe 6.0 lanes, with EENews Europe separately confirming the chip’s 16-channel DDR5 memory controller and over 1.6 TB/s of aggregate bandwidth. (source)
Historical Context: The Road From Naples to Venice
AMD’s EPYC brand has followed a consistent naming pattern since 2017: Naples, Rome, Milan, Genoa, Turin, and now Venice, with new generations arriving roughly every 12 to 18 months. That cadence, sustained without a major delay since the line’s early years, is central to AMD’s pitch to enterprise buyers who lived through Intel’s well-documented process-node delays during the 2016-2020 stretch, when 10nm Xeon parts slipped by years rather than months. Search interest in the older Genoa and Milan chip families remains steady even now, a sign that plenty of that installed base is still in production and due for a refresh cycle Venice, not Intel, is currently positioned to win.
The naming also signals where AMD sees its next fight. “Verano,” the codename already attached to AMD’s 2027 server roadmap, is described in early coverage as either a substantially new design or a refined Zen 6 variant using backside power delivery, a manufacturing technique Intel has already deployed on its own 18A node. (source)
5 Predictions: Where AMD’s Server Momentum Goes From Here
- AMD’s x86 server revenue share likely tests 50% sometime in 2027 if the current pace holds, though gains should slow as AMD’s remaining addressable accounts shrink and Intel defends its largest enterprise contracts more aggressively.
- Diamond Rapids arrives in 2027, not 2026, giving AMD close to a full year of largely uncontested selling at the performance-core high end before Intel can respond in kind.
- HBM4 allocation, not GPU or CPU design, decides how fast Helios racks actually ship through the rest of 2026, and expect more hyperscaler prepayment deals aimed at locking in memory supply ahead of competitors.
- AMD’s stock trades more on hyperscaler capex commentary from Meta, Microsoft and Oracle earnings calls than on Venice benchmark results, since the chip’s revenue impact will not show up in AMD’s own numbers until Q4 2026 at the earliest.
- Arm-based chips keep gaining inside the hyperscalers that design their own silicon even as AMD extends its lead in the merchant x86 market, meaning AMD’s ceiling is capped by how much of the cloud giants’ internal fleets never come up for a competitive bid at all.
Frequently Asked Questions
What is AMD EPYC Venice?
EPYC Venice is AMD’s first Zen 6-based server processor, formally launched July 22-23, 2026 at AMD’s Advancing AI event in San Francisco. It is the first x86 server CPU built in volume on a 2-nanometer-class process and scales up to 256 cores.
When will EPYC Venice actually be available to buy?
AMD confirmed on August 5, 2026 that production ramp of Venice on TSMC’s 2nm process is underway, keeping the company on track for its Q3 2026 shipping target, and ChosunBiz reported on July 24, 2026 that EPYC 9006-series SP7 chips had already reached mass production, with full 256-core, 512-thread configurations shipping starting Q4 2026 on the SP7 socket and entry-level SP8-socket systems following in the first half of 2027, per TechPowerUp, though allocation for accelerator-paired Helios racks may lag behind CPU-only orders because of HBM4 memory supply constraints.
How many cores does EPYC Venice have?
Up to 256 cores and 512 threads across eight compute dies and two I/O dies, up from a 192-core ceiling on the previous Turin generation, with the flagship EPYC 9996 SKU pairing that core count with 128 PCIe 6.0 lanes, 1,024MB of L3 cache and a 4.1GHz boost clock, per a September 2026 spec rundown from The Register and EENews Europe, which also credited the chip’s 16-channel DDR5 design with pushing aggregate memory bandwidth past 1.6 TB/s.
What is AMD’s current server CPU market share?
Mercury Research put AMD’s EPYC line at a record 46.2% of x86 server CPU revenue in Q1 2026, up from 39.5% a year earlier, with a 33.2% share of units sold in the same quarter.
How does EPYC Venice compare to Intel’s Xeon 6 lineup?
Venice’s 256-core ceiling beats Intel’s currently shipping Granite Rapids (128 cores) and Sierra Forest (144 cores), though Intel’s newer Clearwater Forest chip reaches 288 cores on its own 18A process. Intel’s more direct performance-core answer, Diamond Rapids, has no confirmed 2026 launch date.
What is Helios and how does it relate to Venice?
Helios is AMD’s first rack-scale AI system, combining Venice CPUs with Instinct MI450-series GPU accelerators and AMD networking gear into a single deployable unit positioned against Nvidia’s Vera Rubin platform.
What is Venice-X?
Venice-X is a high-performance-computing variant of the Zen 6 server chip, due in the second half of 2027, with 96 cores, 1,152MB of 3D V-Cache and boost clocks up to 5.15GHz, aimed at cache-sensitive HPC workloads rather than general-purpose core density.
Which companies have committed to buying EPYC Venice or Helios hardware?
AMD has pointed to gigawatt-scale compute commitments from Meta and OpenAI, a confirmed MI450-series partnership with Oracle, and a role for Venice and Instinct MI430X GPUs in a U.S. Department of Energy supercomputer, alongside Turin’s existing footprint at Google Cloud, Microsoft Azure and Amazon EC2.
Related Coverage
For more on the chip and cloud infrastructure race shaping 2026, see our related coverage:
- AMD MI350P vs Nvidia H200: 40% Faster, $30K Price [2026]
- TSMC Earnings Jump 77%, Capex Hits $64B [2026]
- AWS Graviton vs Intel/AMD: 45% Cheaper, 25% Faster [2026]
- Nvidia, SK Hynix Ink $500B AI Memory Deal [2026]
- Qualcomm’s Dragonfly C1000 Lands Meta, Eyes $15B [2026]
- RAM Prices Jump 63% as DRAM Hits Record $20 a Chip [2026]
