Unified Video Decoder

Unified Video Decoder (UVD, previously called Universal Video Decoder) is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1.

UVD was introduced with the Radeon HD 2000 Series and is integrated into some of AMD's GPUs and APUs. UVD occupies a considerable amount of the die surface at the time of its introduction^[1] and is not to be confused with AMD's Video Coding Engine (VCE).

As of AMD Raven Ridge (released January 2018), UVD and VCE were succeeded by Video Core Next (VCN).

Overview

The UVD is based on an ATI Xilleon video processor, which is incorporated onto the same die as the GPU and is part of the ATI Avivo HD for hardware video decoding, along with the Advanced Video Processor (AVP). UVD, as stated by AMD, handles decoding of H.264/AVC, and VC-1 video codecs entirely in hardware.

The UVD technology is based on the Cadence Tensilica Xtensa^[2] processor,^[3]^[4]^[5] which was originally licensed by ATI Technologies Inc. in 2004.^[6]

UVD/UVD+

In early versions of UVD, video post-processing is passed to the pixel shaders and OpenCL kernels. MPEG-2 decoding is not performed within UVD, but in the shader processors. The decoder meets the performance and profile requirements of Blu-ray and HD DVD, decoding H.264 bitstreams up to a bitrate of 40 Mbit/s. It has context-adaptive binary arithmetic coding (CABAC) support for H.264/AVC.

Unlike video acceleration blocks in previous generation GPUs, which demanded considerable host-CPU involvement, UVD offloads the entire video-decoder process for VC-1 and H.264 except for video post-processing, which is offloaded to the shaders. MPEG-2 decode is also supported, but the bitstream/entropy decode is not performed for MPEG-2 video in hardware.

Previously, neither ATI Radeon R520 series' ATI Avivo nor NVidia Geforce 7 series' PureVideo assisted front-end bitstream/entropy decompression in VC-1 and H.264 - the host CPU performed this work.^[7] UVD handles VLC/CAVLC/CABAC, frequency transform, pixel prediction and inloop deblocking, but passes the post processing to the shaders.^[8] Post-processing includes denoising, de-interlacing, and scaling/resizing. AMD has also stated that the UVD component being incorporated into the GPU core only occupies 4.7 mm² in area on 65 nm fabrication process node.

A variation on UVD, called UVD+, was introduced with the Radeon HD 3000 series. UVD+ support HDCP for higher resolution video streams.^[9] But UVD+ was also being marketed as simply UVD.

UVD 2

The UVD saw a refresh with the release of the Radeon HD 4000 series products. The UVD 2 features full bitstream decoding of H.264/MPEG-4 AVC, VC-1, as well as iDCT level acceleration of MPEG2 video streams. Performance improvements allow dual video stream decoding and Picture-in-Picture mode. This makes UVD2 full BD-Live compliant.

The UVD 2.2 features a re-designed local memory interface and enhances the compatibility with MPEG2/H.264/VC-1 videos. However, it was marketed under the same alias as "UVD 2 Enhanced" as the "special core-logic, available in RV770 and RV730 series of GPUs, for hardware decoding of MPEG2, H.264 and VC-1 video with dual-stream decoding". The nature of UVD 2.2 being an incremental update to the UVD 2 can be accounted for this move.

UVD 3

UVD 3 adds support for additional hardware MPEG2 decoding (entropy decode), DivX and Xvid via MPEG-4 Part 2 decoding (entropy decode, inverse transform, motion compensation) and Blu-ray 3D via MVC (entropy decode, inverse transform, motion compensation, in-loop deblocking).^[10]^[11] along with 120 Hz stereo 3D support,^[12] and is optimized to utilize less CPU processing power. UVD 3 also adds support for Blu-ray 3D stereoscopic displays.^{[citation needed]}

UVD 4

UVD 4 includes improved frame interpolation with H.264 decoder.^[13] UVD 4.2 was introduced with the AMD Radeon Rx 200 series and Kaveri APU."X.ORG Radeon UVD (Unified Video Decoder) Hardware-UVD4.2: KAVERI, KABINI, MULLINS, BONAIRE, HAWAII". May 2016.

UVD 5

UVD 5 was introduced with the AMD Radeon R9 285. New to UVD is full support for 4K H.264 video, up to level 5.2 (4Kp60).^[14]

UVD 6

The UVD 6.0 decoder and Video Coding Engine 3.0 encoder were reported to be first used in GPUs based on GCN 3, including Radeon R9 Fury series,^[15]^[16] followed by AMD Radeon Rx 300 Series (Pirate Islands GPU family) and AMD Radeon Rx 400 Series (Arctic Islands GPU family).^[17] The UVD version in "Fiji" and "Carrizo"-based graphics controller hardware is also announced to provide support for High Efficiency Video Coding (HEVC, H.265) hardware video decoding, up to 4K, 8-bits color (H.265 version 1, main profile);^[18]^[19]^[20] and there is support for the 10bit-color HDR both H.265 and VP9 video codec in the AMD Radeon 400 series with UVD 6.3.^[21]^[22]^[23]

UVD 7

The UVD 7.0 decoder and Video Coding Engine 4.0 encoder are included in the Vega-based GPUs.^[24]^[25] But there is still no fixed function VP9 hardware decoding.^[26]

UVD 7.2

AMD's Vega20 GPU, present in the Instinct Mi50, Instinct Mi60 and Radeon VII cards, include VCE 4.1 and two UVD 7.2 instances.^[27]^[28]

VCN 1

Starting with the integrated graphics of the Raven Ridge APU (Ryzen 2200/2400G), the former UVD and VCE have been replaced by the new "Video Core Next" (VCN). VCN 1.0 adds full hardware decoding for the VP9 codec.^[29]

Format support

Unified Video Decoder and Video Core Next decoding/encoding support^[30]^[29]
Implementation		MPEG-1^[a]	H.262 (MPEG-2)	H.263 (MPEG-4 ASP)	VC-1/WMV 9	H.264 (MPEG-4 AVC)^[b]		H.265 (HEVC)		VP9	AV1		JPEG	Maximum resolution	Color depth	AMD Fluid Motion
Implementation		Decoding	Decoding	Decoding	Decoding	Decoding	Encoding	Decoding	Encoding	Decoding	Decoding	Encoding	Decoding	Maximum resolution	Color depth	Frame interpolation
UVD 1.0	RV610, RV630, RV670, RV620, RV635	No	No	No	Yes	Yes	No	No	No	No	No	No	No	2K	8-bit	No
UVD 2.0	RS780, RS880, RV770
UVD 2.2	RV710, RV730, RV740
UVD 2.3	Cedar, Redwood, Juniper, Cypress
UVD 3.0	Palm (Wrestler/Ontario), Sumo (Llano), Sumo2 (Llano)	Yes	Yes	Yes
UVD 3.1	Barts, Turks, Caicos, Cayman, Seymour
UVD 3.2	Aruba (Trinity/Richland), Tahiti						VCE^[A]
UVD 4.0	Cape Verde, Pitcairn															Yes
UVD 4.2	Kaveri, Kabini, Mullins, Bonaire, Hawaii
UVD 5.0	Tonga													4K
UVD 6.0	Carrizo, Fiji							Yes					Yes
UVD 6.2	Stoney														10-bit
UVD 6.3	Polaris, VegaM, Lexa								VCE^[A]
UVD 7.0	Vega10, Vega12
UVD 7.2	Vega20
VCN 1.0	Raven, Picasso						Yes		Yes	Yes
VCN 2.0	Navi10, Navi12, Navi14, Renoir, Cézanne													8K		No
VCN 2.5	Arcturus
VCN 2.6	Aldebaran
VCN 3.0	Navi24						No		No
VCN 3.0	Navi21, Navi22, Navi23						Yes		Yes		Yes
VCN 3.1.0	Van Gogh													?	?	?
VCN 3.1.1	Rembrandt	No	No	No	No									8K	10-bit	No
VCN 3.1.2	Raphael													?	?	?
VCN 4.0	Navi 3x											Yes		?	?	?
Implementation		Decoding	Decoding	Decoding	Decoding	Decoding	Encoding	Decoding	Encoding	Decoding	Decoding	Encoding	Decoding	Maximum resolution	Color depth	Frame interpolation
Implementation		MPEG-1^[a]	H.262 (MPEG-2)	H.263 (MPEG-4 ASP)	VC-1/WMV 9	H.264 (MPEG-4 AVC)		H.265 (HEVC)		VP9	AV1		JPEG	Maximum resolution	Color depth	AMD Fluid Motion

1 2 All MPEG-2 decoders support MPEG-1 CPB
↑ High 10 Profile encoding/decoding isn't supported

1 2 MPEG-4 AVC and HEVC encoding by separate Video Coding Engine

Availability

Most of the Radeon HD 2000 series video cards implement the UVD for hardware decoding of 1080p high definition contents.^[31] However, the Radeon HD 2900 series video cards do not include the UVD (though it is able to provide partial functionality through the use of its shaders), which was incorrectly stated to be present on the product pages and package boxes of the add-in partners' products before the launch of the Radeon HD 2900 XT,^{[citation needed]} either stating the card as featuring ATI Avivo HD or explicitly UVD,^{[citation needed]} which only the former statement of ATI Avivo HD is correct. The exclusion of UVD was also confirmed by AMD officials.^[32]

UVD2 is implemented in the Radeon RV7x0 and R7x0 series GPUs. This also includes the RS7x0 series used for the AMD 700 chipset series IGP motherboards.

Feature overview

APUs

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
	Server	Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne		Raphael
		Entry	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló	Rembrandt	Dragon Range	Phoenix
		Entry	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge												Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge	Dalí	Pollock		Mendocino
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle, Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPU microarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"^[33]	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+^[34]	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	N/a												AM5	N/a	N/a
		Mainstream	N/a					AM4						N/a	AM5	N/a
		Entry	FM1	FM2		FM2+		FM2+^[a], AM4	AM4					N/a
		Basic	N/a														N/a	AM1	N/a			FP5	N/a
	Other		FS1	FS1+, FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			N/a														N/a
Fab. (nm)			GF 32SHP (HKMG SOI)			GF 28SHP (HKMG bulk)				GF 14LPP (FinFET bulk)	GF 12LP (FinFET bulk)	TSMC N7 (FinFET bulk)		TSMC N6 (FinFET bulk)	CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk)	TSMC 4nm (FinFET bulk)	TSMC N40 (bulk)	TSMC N28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF 14LPP (FinFET bulk)		GF 12LP (FinFET bulk)	TSMC N6 (FinFET bulk)
Die area (mm²)			228	246		245		245	250	210^[35]		156	180	210	CCD: (2x) 70 cIOD: 122	178	75 (+ 28 FCH)	107		?	125	149			~100
Min TDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APU TDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node^[b]			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
Max CPU^[c] cores per APU			4									8			16	8	2	4			2			4
Max threads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU^[d]			N/a	v2													v1		v2
BMI1, AES-NI, CLMUL, and F16C			N/a														N/a
MOVBE			N/a														N/a
AVIC, BMI2, RDRAND, and MWAITX/MONITORX			N/a														N/a
SME^[e], TSME^[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			N/a														N/a
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			N/a														N/a
MPK, VAES			N/a														N/a
SGX			N/a														N/a
FPUs per core			1	0.5						1							1				0.5	1
Pipes per FPU			2														2
FPU pipe width			128-bit									256-bit					80-bit	128-bit							256-bit
CPU instruction set SIMD level			SSE4a^[f]	AVX				AVX2							AVX-512		SSSE3	AVX			AVX2
3DNow!			3DNow!+	N/a													N/a
PREFETCH/PREFETCHW
GFNI			N/a														N/a
AMX			N/a														N/a
FMA4, LWP, TBM, and XOP			N/a							N/a							N/a					N/a
FMA3			N/a														N/a
AMD XDNA			N/a														N/a
L1 data cache per core (KiB)			64	16				32									32
L1 data cache associativity (ways)			2	4				8									8
L1 instruction caches per core			1	0.5						1							1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	256	64		128		96	128
L1 instruction cache associativity (ways)			2			3				4		8					2				3	4			8
L2 caches per core			1	0.5						1							1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16		1	2			1			2
L2 cache associativity (ways)			16							8							16					8
Max on-die L3 cache per CCX (MiB)			N/a							4			16		32		N/a						4
Max 3D V-Cache per CCD (MiB)										N/a					64	N/a							N/a
Max total in-CCD L3 cache per APU (MiB)										4		8	16		64								4
Max. total 3D V-Cache per APU (MiB)										N/a					64	N/a							N/a
Max. board L3 cache per APU (MiB)										N/a													N/a
Max total L3 cache per APU (MiB)										4		8	16		128								4
APU L3 cache associativity (ways)										16													16
L3 cache scheme										Victim													Victim
Max. L4 cache			N/a														N/a
Max stock DRAM support			DDR3-1866		DDR3-2133			DDR3-2133, DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200, LPDDR4-4266		DDR5-4800, LPDDR5-6400	DDR5-5200	DDR5-5600, LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866, DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
Max DRAM channels per APU			2														1					2	1	2
Max stock DRAM bandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPU microarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen^[36]				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen^[36]	GCN 5th gen			RDNA 2
GPU instruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set			TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400		538	600	?	847	900	1200	600	1300	1900
Max stock GPU base GFLOPS^[g]			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4		86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine^[h]			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16^[37]		Up to 512:32:8		768:48:8	128:8:4		80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
3D engine^[h]			IOMMUv1			IOMMUv2											IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0^[38]		VCN 2.1^[39]	VCN 2.2^[39]	VCN 3.1		?	UVD 3.0	UVD 4.0	UVD 4.2		UVD 6.2	VCN 1.0			VCN 3.1
Video encoder			N/a	VCE 1.0		VCE 2.0		VCE 3.1		VCN 1.0^[38]		VCN 2.1^[39]	VCN 2.2^[39]	VCN 3.1		?	N/a					VCN 1.0			VCN 3.1

[mpeg1-31] 1 2 All MPEG-2 decoders support MPEG-1 CPB

[h264-32] High 10 Profile encoding/decoding isn't supported

[VCE-33] 1 2 MPEG-4 AVC and HEVC encoding by separate Video Coding Engine

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