不同时钟域的时序问题

1.慢时钟域到快时钟域

检查建立时间和保持时间的检查：

Here are the clock definitions for our example.
create_clock -name CLKM \
-period 20 -waveform {0 10} [get_ports CLKM]
create_clock -name CLKP \
-period 5 -waveform {0 2.5} [get_ports CLKP]

When the clock frequencies are different for the launch flip-flop and the capture flip-flop, STA is performed by first determining a common base period. An example of a message produced when STA is performed on such a design with the above two clocks is given below. The faster clock is
expanded so that a common period is obtained.

Expanding clock 'CLKP' to base period of 20.00
(old period was 5.00, added 6 edges).

set_multicycle_path 4 -setup \
-from [get_clocks CLKM] -to [get_clocks CLKP] -end

set_multicycle_path 3 -hold \
-from [get_clocks CLKM] -to [get_clocks CLKP] -end

The -end option implies that we want to move the endpoint (or capture edge) back by the specified number of cycles, which is that of the capture clock. Instead of -end, the other choice, the -start option, specifies the number of launch clock cycles to move by; the -end option specifies the number of capture clock cycles to move by. The -end is the default for a multicycle setup and the -start is the default for multicycle hold.

In summary, if a setup multicycle of N cycles is specified, then most likely
a hold multicycle of N-1 cycles should also be specified. A good rule of
thumb for multi-frequency multicycle path specification in the case of
paths between slow to fast clock domains is to use the -end option. With
this option, the setup and hold checks are adjusted based upon the clock
cycles of the fast clock.

2.快时钟域到慢时钟域

create_clock -name CLKM \
-period 20 -waveform {0 10} [get_ports CLKM]
create_clock -name CLKP \
-period 5 -waveform {0 2.5} [get_ports CLKP]

There are four setup timing checks possible; see Setup1, Setup2, Setup3 and
Setup4 in the figure. However, the most restrictive one is the Setup4 check.
Here is the path report of this most restrictive path. Notice that the launch
clock edge is at 15ns and the capture clock edge is at 20ns.

Similar to the setup checks, there are four hold checks possible. Figure 8-26
shows the most restrictive hold check which ensures that the capture edge
at 0ns does not capture the data being launched at 0ns. Here is the timing
report for this hold check.

In general, a designer may specify the data path from the fast clock to the
slow clock to be a multicycle path. If the setup check is relaxed to provide
two cycles of the faster clock for the data path, the following is included for
this multicycle specification:

set_multicycle_path 2 -setup \
-from [get_clocks CLKP] -to [get_clocks CLKM] -start
set_multicycle_path 1 -hold \
-from [get_clocks CLKP] -to [get_clocks CLKM] -start
# The -start option refers to the launch clock and is
# the default for a multicycle hold.

Unlike the case of paths from slow to fast clock domains, a good rule of thumb for multi-frequency multicycle path specification in the case of paths from fast to slow clock domains is to use the -start option. The setup
and hold checks are then adjusted based upon the fast clock.