理解DRAM Gear Down模式：提高稳定性的选择

DDR4内存每针的数据传输速度达到每秒1.6G,在原型中传输的最大速率为3.2G,鉴于目前DDR3的传输性能已经达到了1.6GT/s,未来在DDR4的升级过程中将会进一步提升传输速度。其他的DDR4还将传输速度,而且能偶通过应用对内存进行设置。包括一个在DQ串行总线上的伪漏极开路接口,每个DQ的都附带geardown模式能够达到2,667 MT/s或以上,并采用了新的存储架构,内部整合VrefDQ并包括改善过的training模式。

1. DDR—动态随机存储器 2. tRC（row cycle time） --行循环时间 3. tRCD-----从行有效到读/写命令发出之间的时间间隔 4. tRRD（Row active to Row active delay） --行激活到激活延迟时间 5. tCK---时钟周期 6. AL(Additive latency)---附加的潜伏期 7. RL(Read latency)---------- 读选通潜伏期 8. WL(write latency)------ 写选通潜伏期 9. CL（CAS Latency ）----列地址脉冲选通潜伏期 10. tAC（Access Time from CLK）-----时钟触发后的访问时间 11. BL (Burst Lengths)-----突发长度 12. tRP（Row Precharge command Period）-----行预充电有效周期 13. DQS----数据选取脉冲 14. Precharge---预充电 15. Refresh—刷新，AR(auto refresh),SR(self refresh) 16. DLL--延迟锁定回路

这是一份DDR4标准，硬件工程师可能会用到，谢谢

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select the row; refer to “DDR4 SDRAM Addressing” on datasheet). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.